11 of 11 Electronic Design Automation Jobs in England

ASIC Design Engineer Location: London HQ | Fully remote within the UK (quarterly visits) Salary: Up to £80,000 base only I’m currently recruiting for an ASIC Design Engineer on behalf of a leading managed service provider that is partnering with a global semiconductor powerhouse to build … digital logic/RTL design for ASIC or SoC projects. Strong SystemVerilog skills. Solid understanding of digital design fundamentals. Experience using EDA tools for simulation, synthesis, and linting. Familiarity with low-power design techniques, timing analysis, and common interfaces such as AXI, AMBA, PCIe, or DDR. Working ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

level verification. Develop robust SystemVerilog/UVM verification environments. Create and execute tests to achieve high coverage and debug complex failures. Collaborate closely with design teams to deliver high-quality results. Automate verification flows using Python or Perl scripts. What Were Looking For: 7+ years of hands-on experience … strong digital design knowledge. Experience verifying digital systems using standard IP components (e.g., microprocessor cores, hierarchical memory subsystems). Proficiency with EDA simulation and debug tools. Strong scripting skills (Python, Perl). Excellent communication skills and ability to work autonomously. Why This Role is Exciting: This is a fantastic ...

Title: Senior Hardware Verification Engineer Location: England, United Kingdom (Remote anywhere inside the country) About the Role: We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping … years and current hands-on experience in block-level/IP-level/SOC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based testbenches Experience with modern programming languages like Python Knowledge of ARM AMBA protocols such ...

will work with SoC teams, architects, and platform leads to define, influence, and align technical requirements for implementation. Your role will involve assessing design trade-offs and delivering the most optimal solutions for customers and development partners. Key Responsibilities: Collaborate with technical leads, product managers, and SoC development teams … experience with embedded system board design, including complex LSI devices such as FPGAs, embedded firmware, and power management ICs. Competence in using EDA tools for schematic entry and PCB layout (e.g., Cadence OrCAD CIS, Allegro PCB Suite). Strong knowledge of PCB stack-up definition, controlled impedance routing ...

running AMS simulations will all form part of this critical role, together with identifying bugs, and developing new methodologies with the verification team and EDA vendors. The successful Mixed Signal Verification Engineer will have: Proven experience within AMS (Analog Mixed Signal) Verification Expertise in test bench design, behavioral modelling ...

running AMS simulations will all form part of this critical role, together with identifying bugs, and developing new methodologies with the verification team and EDA vendors. The successful Mixed Signal Verification Engineer will have: Proven experience within AMS (Analog Mixed Signal) Verification Expertise in test bench design, behavioral modelling ...

Design Engineer with expertise in Static Timing Analysis (STA) and Timing/SDC constraints, modern semiconductor process technologies and an experienced user of EDA tools. Generous salary package with Hybrid working. This cutting-edge scale-up Semiconductor Company is revolutionizing the electronics industry, enabling the build of high-speed … modern semiconductor process technologies: 14/16nm, 7nm, 5nm and 3nm. Expertise in STA and Timing Constraints. Advanced user of a range of EDA tools. Experience in SDC verification tools. Solid understanding of RTL to GDS implementation flow. Good Scripting skills. The successful Digital Physical Design Engineer will work ...

performance validation boards that support next-generation compute and high-speed interfaces. This is a role for a strategic thinker who can navigate complex design trade-offs to develop optimal solutions for our customers and development partners. Key Responsibilities Architectural Definition: Translate complex technical requirements from SoC teams … LPDDR5/6 . Complex Board Design: Proven competence in designing boards with high-complexity LSI devices (FPGAs), embedded firmware, and PMICs. EDA Proficiency: Expert-level understanding of the Cadence OrCAD CIS and Allegro PCB suite . Advanced PCB Knowledge: Strong command of PCB stack-up definition and controlled ...

configuration deployments. Execute and monitor Windows services and command-line operations to support TCU deployment and maintenance. Support integration between Teamcenter, Creo (IPEM interface), EDA, Component Information system, SAP S/4HANA and Siemens Opscenter ensuring data consistency and process alignment across PLM, MES, and ERP systems. Document deployment processes … Experience in remote collaboration and screen sharing for technical troubleshooting. Experience integrating PLM with engineering tools, MES and ERP systems, particularly Polarion, Creo, Siemens EDA, Opscenter and SAP S/4HANA. Proven experience with Siemens toolset, especially Teamcenter, Opscenter and Polarion. Strong understanding of PLM deployment lifecycle and configuration management. ...

Design Engineer with expertise in Static Timing Analysis (STA) and Timing/SDC constraints, modern semiconductor process technologies and an experienced user of EDA tools. Generous salary package with Hybrid working. This cutting-edge scale-up Semiconductor Company is revolutionizing the electronics industry, enabling the build of high... ...