1 to 25 of 31 Electronic Design Automation Jobs in England

integration Oversee resource planning, project schedules, budgets and delivery milestones Mentor, coach and technically develop IC design engineers Represent the digital team in EDA tool selection and methodology decisions Collaborate across global engineering teams to ensure seamless design flow Support silicon debug, failure analysis and validation activities Knowledge … full digital IC design lifecycle from specification to silicon Experience with low-power design and power management techniques Solid understanding of EDA tools and digital design flows through to timing sign-off Knowledge of DfT, DfM, silicon debug and failure analysis methodologies Strong communication skills with ...

ASIC Design Engineer Location: London HQ | Fully remote within the UK (quarterly visits) Salary: Up to £80,000 base only I’m currently recruiting for an ASIC Design Engineer on behalf of a leading managed service provider that is partnering with a global semiconductor powerhouse to build … digital logic/RTL design for ASIC or SoC projects. Strong SystemVerilog skills. Solid understanding of digital design fundamentals. Experience using EDA tools for simulation, synthesis, and linting. Familiarity with low-power design techniques, timing analysis, and common interfaces such as AXI, AMBA, PCIe, or DDR. Working ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

knowledge, experience and further your career development. The successful candidates will be able to and open to learn other areas and specialisms outside ASIC Design and Verification from RTL Design, Formal Verification and DevOps. The successful candidate will also be working directly for an industry renowned Senior Director … engineers. Opportunity to become a mentor to your colleagues. Understanding of different parts of the design & verification cycle. Experience working with leading edge EDA tools and process nodes using industry standard languages and methodologies (e.g. Systemverilog, UVM, Formal). Working on high volume data centre & enterprise products used ...

level verification. Develop robust SystemVerilog/UVM verification environments. Create and execute tests to achieve high coverage and debug complex failures. Collaborate closely with design teams to deliver high-quality results. Automate verification flows using Python or Perl scripts. What Were Looking For: 7+ years of hands-on experience … strong digital design knowledge. Experience verifying digital systems using standard IP components (e.g., microprocessor cores, hierarchical memory subsystems). Proficiency with EDA simulation and debug tools. Strong scripting skills (Python, Perl). Excellent communication skills and ability to work autonomously. Why This Role is Exciting: This is a fantastic ...

Title: Senior Hardware Verification Engineer Location: England, United Kingdom (Remote anywhere inside the country) About the Role: We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping … years and current hands-on experience in block-level/IP-level/SOC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based testbenches Experience with modern programming languages like Python Knowledge of ARM AMBA protocols such ...

will work with SoC teams, architects, and platform leads to define, influence, and align technical requirements for implementation. Your role will involve assessing design trade-offs and delivering the most optimal solutions for customers and development partners. Key Responsibilities: Collaborate with technical leads, product managers, and SoC development teams … experience with embedded system board design, including complex LSI devices such as FPGAs, embedded firmware, and power management ICs. Competence in using EDA tools for schematic entry and PCB layout (e.g., Cadence OrCAD CIS, Allegro PCB Suite). Strong knowledge of PCB stack-up definition, controlled impedance routing ...