24 of 24 Field-Programmable-Gate-Array Jobs in London

performance efficiency Design security-hardened digital circuits with awareness of side channel vulnerabilities and appropriate countermeasures Deliver production ready designs targeting both ASIC and FPGA platforms Own the design lifecycle: specification, micro-architecture, coding (Verilog/VHDL), synthesis, timing closure, and verification Support design activities through scripting and automation (Python ...

C++ developer to be part of the low latency development team. The team provides industry leading low-latency trading services for our clients, utilizing FPGA, C++ and Java technologies. The candidate will be focusing on the C++ components. The ideal candidate: Is motivated by working in a high performing team ...

within a finance (or games) environment You have a good understanding of low level system design, Operating Systems, Networking, Socket Level programming, hardware, compliers, FPGA You achieved a 2.1 or above in Computer Science from a top tier university You are collaborative and pragmatic with great communication and stakeholder management ...

NUMA, CPU affinity, and custom memory management. Proven track record of building latency-critical systems in trading, gaming, or telecom environments. Bonus: Experience with FPGA acceleration, RDMA, or custom NIC firmware. Why Apply? Work with some of the fastest systems and smartest minds in the industry. Direct impact on trading ...

getting in touch because I’m supporting a client who are pushing the boundaries of high-performance IP on next generation FPGA and Adaptive SoC platforms and your experience looks highly relevant. They require someone with strong SystemVerilog RTL capability, confident across 100Gb Ethernet, PCIe Gen5 and AXI, and comfortable ...

getting in touch because I’m supporting a client who are pushing the boundaries of high-performance IP on next generation FPGA and Adaptive SoC platforms and your experience looks highly relevant. They require someone with strong SystemVerilog RTL capability, confident across 100Gb Ethernet, PCIe Gen5 and AXI, and comfortable ...

site visits. Key Responsibilities Design, develop, and verify digital hardware modules for high-security applications. Create robust designs suitable for both ASIC and FPGA implementations. Contribute to the full digital design lifecycle, from concept through to deployment. Develop hardware architectures supporting cryptographic functionality. Qualifications Bachelor’s or Master’s degree ...

site visits. Key Responsibilities Design, develop, and verify digital hardware modules for high-security applications. Create robust designs suitable for both ASIC and FPGA implementations. Contribute to the full digital design lifecycle, from concept through to deployment. Develop hardware architectures supporting cryptographic functionality. Qualifications Bachelor’s or Master’s degree ...

within a finance (or games) environment You have a good understanding of low level system design, Operating Systems, Networking, Socket Level programming, hardware, compliers, FPGA You achieved a 2.1 or above in Computer Science from a top tier university You are collaborative and pragmatic with great communication and stakeholder management ...

within a finance (or games) environment You have a good understanding of low level system design, Operating Systems, Networking, Socket Level programming, hardware, compliers, FPGA You achieved a 2.1 or above in Computer Science from a top tier university You are collaborative and pragmatic with great communication and stakeholder management ...

work on next-generation market-making and arbitrage strategies. The Role: You would be joining a high-P&L, cross-functional team (Traders, Quants, FPGA Engineers) to build execution logic and order management systems where nanoseconds determine profitability. Location & Flexibility: This team is operationally distributed across major hubs. ...

FPGA ENGINEER – ULTRA-LOW LATENCY SYSTEMS Location: London (Hybrid: 4 days onsite) Sector: Quant Trading/High-Performance Computing Quant Capital is partnering with a global trading firm building a greenfield FPGA team focused on low-latency, high-throughput hardware systems. This small, senior group will deliver high-speed compute … infrastructure integrated directly into trading, research, and networking pipelines. What You’ll Be Doing Designing and implementing latency-optimised FPGA systems in Verilog/SystemVerilog Developing high-speed modules (PCIe, Ethernet, DDR/QDR) with deep pipelining Using simulation and formal tools (Verilator, Cocotb, etc.) for validation Working across teams ...

FPGA ENGINEER – ULTRA-LOW LATENCY SYSTEMS Location: London (Hybrid: 4 days onsite) Sector: Quant Trading/High-Performance Computing Quant Capital is partnering with a global trading firm building a greenfield FPGA team focused on low-latency, high-throughput hardware systems. This small, senior group will deliver high-speed compute … infrastructure integrated directly into trading, research, and networking pipelines. What You’ll Be Doing Designing and implementing latency-optimised FPGA systems in Verilog/SystemVerilog Developing high-speed modules (PCIe, Ethernet, DDR/QDR) with deep pipelining Using simulation and formal tools (Verilator, Cocotb, etc.) for validation Working across teams ...

trading environments. Proficient in Rust Experience with SQL databases. Familiarity with functional and component testing. Experience in crypto exchange connectivity and/or FPGA technologies is a plus. Knowledge of gRPC and Node.js interaction is strongly preferred. Experience in High-Frequency Options Trading or low-latency options systems is advantageous ...

looking for a Principal FPGA Design Engineer to lead complex FPGA developments from system requirements through to fully verified hardware. This is a senior, hands-on technical leadership role within a high-performance engineering team. Key Responsibilities Lead FPGA architecture and end-to-end VHDL design Define system-level requirements … plans, and documentation Support and enhance existing firmware Lead design reviews and release activities Mentor junior engineers and provide technical leadership Requirements Ten years FPGA design experience Proven experience with multi-FPGA systems Strong system architecture and requirements decomposition skills Experience with Radar or DSP applications ...

work collaboratively in a multidisciplinary environment. Key Responsibilities Develop and maintain embedded software, SDKs, and firmware for imaging systems Integrate drivers, APIs, and FPGA-based architectures Collaborate with hardware engineers on system integration and testing Debug and troubleshoot across hardware/software layers Contribute to the full product lifecycle from … concept to deployment Mentor junior engineers and support process improvement Essential Criteria Strong skills in C/C++, RTOS. Experience with FPGA integration and communication protocols (SPI, I2C, UART, Ethernet, USB) Solid debugging and problem-solving abilities 3+ years' experience in embedded/software development Benefits Competitive salary + performance ...

Do you want to work on some of the most advanced technology in the world? Our client operates one of the most powerful private HPC clusters globally, with 10s of thousands of GPUs (including 1000s ...

Do you want to work on some of the most advanced technology in the world? Our client operates one of the most powerful private HPC clusters globally, with 10s of thousands of GPUs (including 1000s ...

influence trading performance. Expect a hands-on, fast-paced environment where technical depth, innovation, and collaboration are key. You’ll architect, implement and deploy FPGA solutions across the business. They’re a global trading firm with offices in both the UK & US, the team is lean (~40 people globally), meaning … direct impact of your work – no red tape here! You’ll also enjoy a lot of autonomy, focusing on building new FPGA applications from the ground up – including RTL design, synthesis, and timing analysis whilst working closely with Traders and Developers to identify performance bottlenecks and create cutting-edge solutions. ...

influence trading performance. Expect a hands-on, fast-paced environment where technical depth, innovation, and collaboration are key. You’ll architect, implement and deploy FPGA solutions across the business. They’re a global trading firm with offices in both the UK & US, the team is lean (~40 people globally), meaning … direct impact of your work – no red tape here! You’ll also enjoy a lot of autonomy, focusing on building new FPGA applications from the ground up – including RTL design, synthesis, and timing analysis whilst working closely with Traders and Developers to identify performance bottlenecks and create cutting-edge solutions. ...

most prestigious high-frequency trading companies in the world to find a verification engineer to help verify their complex low-latency FPGA systems. You'll be joining a team at the forefront of innovation in design verification, where you'll be supported in pushing the envelope alongside top pioneers … analytical capability, able to isolate and resolve complex RTL and testbench issues efficiently. At least two years of professional RTL functional verification experience for FPGA or ASIC designs. Hands-on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis. Proficiency in Python ...

most prestigious high-frequency trading companies in the world to find a verification engineer to help verify their complex low-latency FPGA systems. You'll be joining a team at the forefront of innovation in design verification, where you'll be supported in pushing the envelope alongside top pioneers … analytical capability, able to isolate and resolve complex RTL and testbench issues efficiently. At least two years of professional RTL functional verification experience for FPGA or ASIC designs. Hands-on expertise in SystemVerilog and UVM, including stimulus development and code/functional coverage collection and analysis. Proficiency in Python ...

contested ground and every cache miss is a bug. Location: London/New York/Chicago Environment: C++20/23 • Linux • Kernel-bypass Networking • FPGA • RDMA • Nanosecond Execution Their engineers operate where nanoseconds decide P&L — measured, profiled, and deployed in live markets where performance is the edge. They … handlers and SIMD-vectorized pricing logic in AVX-512 . Deliver next-tick telemetry with nanosecond-precision timestamps and cross-core synchronization. Collaborate with FPGA specialists to merge hardware precision with software agility. The Toolkit Modern C++20/23 , template metaprogramming, constexpr, inline assembly when necessary. Profiling and optimization using ...

contested ground and every cache miss is a bug. Location: London/New York/Chicago Environment: C++20/23 • Linux • Kernel-bypass Networking • FPGA • RDMA • Nanosecond Execution Their engineers operate where nanoseconds decide P&L — measured, profiled, and deployed in live markets where performance is the edge. They … handlers and SIMD-vectorized pricing logic in AVX-512 . Deliver next-tick telemetry with nanosecond-precision timestamps and cross-core synchronization. Collaborate with FPGA specialists to merge hardware precision with software agility. The Toolkit Modern C++20/23 , template metaprogramming, constexpr, inline assembly when necessary. Profiling and optimization using ...