Berkshire, South East, United Kingdom Hybrid / WFH Options
Defence
Ability to provide technical leadership to a team of Firmware engineers in the design and development of FPGAs. Thorough experience of using Xilinx, Lattice, Altera or Microsemi FPGAs and their associated development tool chains. Proficient in Verification. Good knowledge of FPGA EDA tools and tool flow. Proficient in more »
for video processing and analytics applications. The primary FPGA platforms used are the Xilinx Zynq and Zynq UltraScale+ families, however other Xilinx and Lattice devices are also used where required. You will collaborate in the development of complex systems including requirements analysis, concept development and design, implementation and more »
be able to demonstrate a sound understanding of the principals involved Verilog design on a range of FPGA and SOC devices (Xilinx, MicroSemi, Lattice, Altera). Experience of working in multi-disciplinary teams on fast paced projects is expected. Experience of working in A multi-disciplinary teams on more »
be able to demonstrate a sound understanding of the principals involved Verilog design on a range of FPGA and SOC devices (Xilinx, MicroSemi, Lattice, Altera). Experience of working in multi-disciplinary teams on fast paced projects is expected. Experience of working in A multi-disciplinary teams on more »
Rickmansworth, Hertfordshire, South East, United Kingdom
Hunter Selection
be able to demonstrate a sound understanding of the principals involved Verilog design on a range of FPGA and SOC devices (Xilinx, MicroSemi, Lattice, Altera). Experience of working in multi-disciplinary teams on fast paced projects is expected. Experience of working in A multi-disciplinary teams on more »
given * Modification of existing firmware designs and test benches Desirable Skills, Qualifications & Knowledge: * Using FPGA technologies especially from either Xilinx, Microsemi (Actel) or Lattice and their tools * Advanced verification techniques using either VHDL or System Verilog/UVM * Specifying complex timing and area constraints for efficient FPGA place more »
