Senior Silicon Design Engineer
- Hiring Organisation
- Advanced Micro Devices
- Location
- Cheltenham, Gloucestershire, UK
- Employment Type
- Full-time
SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...