7 of 7 Perl Jobs in the West Midlands

understanding of change management process Should have good understanding of Windows server level commands Should have good experience on writing scripts at server level (Perl script/VB script/Java script/batch scripts) Person Specification Should have performed developer role in past experience Should have worked for international ...

maintain restore procedures. -Configure and manage PowerHA SystemMirror clusters. -Work with SAN storage (NPIV), PowerVC, and virtualization technologies. -Develop automation scripts using UNIX Shell, Perl, or Python. -Experience in Hardware/Firmware Upgrade/Refresh/Migration -Ensure compliance with ITIL processes and security standards. -Should have Proficiency in Scripting ...

from simulation to post-silicon What We're Looking For Experience in digital IC design verification (SystemVerilog/UVM) Knowledge of Python/C++ (Perl/TCL a plus) Understanding of computer architecture, memory hierarchies, and bus protocols (AMBA/AXI, NoC) Bachelor's or Master's in Electrical Engineering ...

simulation tools (e.g., Synopsys VCS, Cadence Xcelium) Solid understanding of digital design principles, RTL design, and ASIC development flows Experience with scripting languages (Python, Perl, Shell, etc.) Familiarity with formal verification, assertion-based verification, and coverage-driven verification techniques Excellent problem-solving skills and attention to detail What ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...

SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench development Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus Proficiency ...