in digital IC design backend flow synthesis, STA, test insertion, MBIST, formality, GDS layout etc Experience in EDA tools for custom IC development like Siemens Questa for simulation and verification, Synopsys DesignCompiler for synthesis and STA, Spyglass for linting, etc. Experience in writing IP design specifications and block level more »
119k (depending on experience) What you need to be successful in this role: Experience writing Hardware description languages ideally SystemVerilog Experience using EDA simulators (Siemens, Synopsys, Cadence) Experience working with version control and code review systems (Git, Gerrit) Experience with CI (Jenkins) Scripting for design automation (Python, Perl, JSON more »
Cambridge, Cambridgeshire, East Anglia, United Kingdom
Langham Recruitment Limited
Stream, etc). Experience with Linux OS, revision control (Git) and scripting languages (Bash, Tcl, and Python). Experience with EDA tools for simulation (Siemens Quest), Synthesis (DesignCompiler). Salary and Benefits: Up to £100K salary DOE. Travel opportunities. Private Health Insurance. Life insurance. 25 holidays plus public holidays more »
experience in architecting/implementing formal verification environments. Experience in SVA and PSL. Experience working with industry-leading formal tools. eg. Cadence, Jasper Gold, Siemens EDA QuestaFormal, or Synopsys. Keywords: Formal Verification/Semiconductor/Semi conductor/Semi-conductor/GPU/SystemVerilog/System Verilog Assertions/… Property Specification Language/Cadence/JasperGold/Siemens EDA/Synopsys If you are interested in this Formal Verification Engineer position, please send a CV to ts@eu-recruit.com By applying to this role you understand that we may collect your personal data and store and process it more »
