equivalent) candidates with significant experience in FPGA development. Proficient in VHDL language and Design Skills. (Highly essential) Proficient in verification skills using VHDL and SystemVerilog methodologies. (Highly essential) Extensive experience designing for Xilinx, Intel, or Microsemi FPGAs. Experience in professional configuration and documentation of designs. Experience working as part of more »
Key Skills MSc/PhD with 10+ years of industrial experience in leading the design of complex digital IP/SoCs Strong experience in SystemVerilog, Verilog, and/or VHDL Strong experience in designing signal processing, datapaths, interfaces, interconnects Strong knowledge of clock domain crossing (CDC) techniques, asynchronous design techniques more »
Stevenage, Hertfordshire, South East, United Kingdom
Guidant Global
equivalent) candidates with significant experience in FPGA development. Proficient in VHDL language and Design Skills. (Highly essential) Proficient in verification skills using VHDL and SystemVerilog methodologies. (Highly essential) Extensive experience designing for Xilinx, Intel, or Microsemi FPGAs. Experience in professional configuration and documentation of designs. Experience working as part of more »
Employment Type: Contract
Rate: £65 - £90 per hour + In IR35 (PAYE & Umbrella available) DOE
driver development Comprehensive understanding of clock domain crossing techniques Strong knowledge of FPGA tool flows (synthesis, partitioning, place&route, timing analysis) Excellent skills in SystemVerilog/Verilog/VHDL Experience in scripting (tcl preferable) and Python programming Experience using Questa, ModelSim, GHDL, Verilator, cocotb Experience using Quartus/Vivado/ more »
computer science Minimum 5 years of experience in digital ASIC design for advanced CMOS technology nodes Excellent programming skills in hardware description languages (e.g. SystemVerilog) Excellent knowledge of state-of-the-art SoC design flows (Cadence/Synopsys/Siemens-Mentor) Good programming skills in scripting languages like Python, Perl more »
working with scripting languages like Python, Tcl, Make files, bash etc. Required Skills and Experience : Excellent theoretical and practical experience of RTL Verification utilising SystemVerilog, including SVA. Proficiency in C programming plus, ideally, some grounding in assembly language (ideally Arm assembler) and object-orientated coding (e.g. C++) Skilled in simulation more »
Cambridge, England, United Kingdom Hybrid / WFH Options
Vivid Resourcing
Experience: Track record of delivering RTL designs in a SoC or FPGA context. Skilled in RTL Verification at both unit and system level, using SystemVerilog, including SVA. Proficiency in C programming plus, ideally, some grounding in assembly language (ideally Arm assembler) and object-orientated coding (e.g. C++) Experience of ASIC more »
such as shell scripting and basic Perl scripts Ability to work with technical writers in the production of technical documentation. Tools/Technologies Verilog, SystemVerilog, Perl Shell scripting, Python, Sage, Tcl C, C++ MATLAB, Xilinx Vivado Unix, Linux Front-end ASIC design tools - synopsys/cadence/mentor Excellent salary more »
requirements into micro-architecture • VHDL, Verilog HDL coding • Digital simulation using Modelsim/Questa or similar • Experience with designer-level test bench (VHDL or SystemVerilog) • Familiarity with revision control (git, cvs, clearcase, etc.) • Working knowledge of internal logic analyzer (ILA/chipscope/signaltap) • Experience and willingness for lab testing … EDA tools and flows (Synopsys, Cadence, etc.) • Experience in leading a design team • Experience in hardware design and hands-on lab debug • Experience with SystemVerilog/UVM • Experience with generating scripts (Perl, Tcl, Python, etc.) • Working knowledge of C/C++ • Experience with interfaces: ADC/DACs, SerDes, PCIe, JTAG more »
Electrical/Electronic Engineering or a related field. Brings 3+ years of hands-on experience in RTL design and verification for FPGAs, mastering Verilog, SystemVerilog, or VHDL. Proficient in FPGA toolchains, especially with Xilinx Vivado (preferred) or Intel Quartus. Skilled in simulation environments, preferably with expertise in Modelsim/Questa. more »
highly skilled, close-knit team. Key Responsibilities: Digital design development for custom IC Integration including the writing of IP design specifications, coding Verilog and SystemVerilog models for simulation, synthesis and static timing analysis and writing automated simulation and verification build scripts. Building automated pre-silicon verification environment whilst supporting early more »
Cambridge, Cambridgeshire, East Anglia, United Kingdom
Langham Recruitment Limited
highly skilled, close-knit team. Key Responsibilities: Digital design development for custom IC Integration including the writing of IP design specifications, coding Verilog and SystemVerilog models for simulation, synthesis and static timing analysis and writing automated simulation and verification build scripts. Building automated pre-silicon verification environment whilst supporting early more »
Cambridge, England, United Kingdom Hybrid / WFH Options
Codasip
work Requirements YOU SHOULD HAVE: Over 10 years of recent and relevant module design experience with at least one HDL (VHDL/Verilog/SystemVerilog) Good knowledge of CPU architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning tools more »
working closely with a skilled and diverse team, and developing the environment. Must-have experience: Circa 5+ years' experience in FPGA development VHDL/SystemVerilog RTL design/coding Tcl/Python or similar coding/scripting (Nice-to-have experience): UVM verification embedded software/firmware DevOps/software more »
Key Skills/Experience: Degree in Electronic Engineering or another relevant discipline ASIC Design & Implementation FPGA development Broad knowledge of Digital Design Verilog/SystemVerilog/VHDL Any mix of the following is nice to have: Xilinx FPGAs Design synthesis, static timing analysis, digital block routing etc. Cadence Virtuoso Benefits more »
PhD in electrical engineering or computer science Minimum 5 years of experience in digital ASIC design Excellent programming skills in hardware description languages (e.g. SystemVerilog) Good programming skills in scripting languages (e.g. Python, Perl, Tcl) Expertise in verification methodologies & tools (e.g. UVM) would be a plus Excellent written and verbal more »
Greater Bristol Area, United Kingdom Hybrid / WFH Options
IC Resources
enhancing Verification strategy and architecture of IP testbenches. Key Skills At least 8 years of experience in Verification working with Verilog and/or SystemVerilog; 5 years of experience on IP/block level Test-bench bring up on SV UVM based platform; The ability to understand complex design specification more »
of cutting edge, high-performance computing processors! We are particularly looking for engineers with experience in: Verification and/or design of complex SoC SystemVerilog/UVM/VHDL SystemC/C++ Embedded C scripting languages like Bash/Perl/Python Experience in the following are a plus: Experience more »
Implementing Regression tests Performing Formal Verification Working closely with IC designers and post-silicon engineers Qualifications and Background Requirements: Knowledge/experience with HDL (SystemVerilog/Verilog/VHDL), particularly for testbenches creation Knowledge/experience in scripting languages, such as Tcl and Python Some knowledge of ASIC design flow more »
help develop digital designs for custom IC integration and design and validate new silicon designs. Experience: Experience in ASIC or FPGA Design Strong Verilog, SystemVerilog experience Python experience CPU architecture is a plus. You will be part of a company where the work environment is stimulating and exciting, as you more »
/Physics etc. Processor architecture, ARM, CPU, RISC-V etc SOC design and architecture, IP integration Confident ability in RTL design (Verilog/VHDL , SystemVerilog) for ASIC/FPGA Proven ability in tape-out and IP development and delivery processes Bonus/"nice-to-have" skills: High Speed Communication, Protocols more »
Science or similar A number of years’ experience working on the verification phase for digital ASICs Hands on experience in VHDL/Verilog/SystemVerilog Code/script development experience using assembler, perl, C/C++. An ability to learn quickly and work unsupervised or as part of a team more »
Electronic Engineering or similar A proven background working as a Digital IC Design Engineer, with solid hands-on skills in RTL design - Verilog/SystemVerilog (circa 5-10+ years' experience), and digital-analog integration A good handle on ASIC Verification activities Physical implementation knowledge Excellent communication skills in English more »
team members, in collaboration with our international team(s) The ideal candidates for this position will have: Delivered with (as applicable) SoC design verification, SystemVerilog languages (UVM, SVA, SFC), low power verification (UPF methodology), software/hardware co-verification (SystemC/C/C++), Interfaced with designs/teams with more »
to enhancing Verification strategy and architecture of IP testbenches.Key Skills At least 8 years of experience in Verification working with Verilog and/or SystemVerilog; 5 years of experience on IP/block level Test-bench bring up on SV UVM based platform; The ability to understand complex design specification more »
