equivalent) candidates with significant experience in FPGA development. Proficient in VHDL language and Design Skills. (Highly essential) Proficient in verification skills using VHDL and SystemVerilog methodologies. (Highly essential) Extensive experience designing for Xilinx, Intel, or Microsemi FPGAs. Experience in professional configuration and documentation of designs. Experience working as part of more »
Stevenage, Hertfordshire, South East, United Kingdom
Guidant Global
equivalent) candidates with significant experience in FPGA development. Proficient in VHDL language and Design Skills. (Highly essential) Proficient in verification skills using VHDL and SystemVerilog methodologies. (Highly essential) Extensive experience designing for Xilinx, Intel, or Microsemi FPGAs. Experience in professional configuration and documentation of designs. Experience working as part of more »
Employment Type: Contract
Rate: £65 - £90 per hour + In IR35 (PAYE & Umbrella available) DOE
driver development Comprehensive understanding of clock domain crossing techniques Strong knowledge of FPGA tool flows (synthesis, partitioning, place&route, timing analysis) Excellent skills in SystemVerilog/Verilog/VHDL Experience in scripting (tcl preferable) and Python programming Experience using Questa, ModelSim, GHDL, Verilator, cocotb Experience using Quartus/Vivado/ more »
working with scripting languages like Python, Tcl, Make files, bash etc. Required Skills and Experience : Excellent theoretical and practical experience of RTL Verification utilising SystemVerilog, including SVA. Proficiency in C programming plus, ideally, some grounding in assembly language (ideally Arm assembler) and object-orientated coding (e.g. C++) Skilled in simulation more »
Cambridge, England, United Kingdom Hybrid / WFH Options
Vivid Resourcing
Experience: Track record of delivering RTL designs in a SoC or FPGA context. Skilled in RTL Verification at both unit and system level, using SystemVerilog, including SVA. Proficiency in C programming plus, ideally, some grounding in assembly language (ideally Arm assembler) and object-orientated coding (e.g. C++) Experience of ASIC more »
Electrical/Electronic Engineering or a related field. Brings 3+ years of hands-on experience in RTL design and verification for FPGAs, mastering Verilog, SystemVerilog, or VHDL. Proficient in FPGA toolchains, especially with Xilinx Vivado (preferred) or Intel Quartus. Skilled in simulation environments, preferably with expertise in Modelsim/Questa. more »
highly skilled, close-knit team. Key Responsibilities: Digital design development for custom IC Integration including the writing of IP design specifications, coding Verilog and SystemVerilog models for simulation, synthesis and static timing analysis and writing automated simulation and verification build scripts. Building automated pre-silicon verification environment whilst supporting early more »
Cambridge, Cambridgeshire, East Anglia, United Kingdom
Langham Recruitment Limited
highly skilled, close-knit team. Key Responsibilities: Digital design development for custom IC Integration including the writing of IP design specifications, coding Verilog and SystemVerilog models for simulation, synthesis and static timing analysis and writing automated simulation and verification build scripts. Building automated pre-silicon verification environment whilst supporting early more »
Bristol, England, United Kingdom Hybrid / WFH Options
Codasip
work Requirements YOU SHOULD HAVE: Over 10 years of recent and relevant module design experience with at least one HDL (VHDL/Verilog/SystemVerilog) Good knowledge of CPU architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning tools more »
Cambridge, England, United Kingdom Hybrid / WFH Options
Codasip
work Requirements YOU SHOULD HAVE: Over 10 years of recent and relevant module design experience with at least one HDL (VHDL/Verilog/SystemVerilog) Good knowledge of CPU architecture Ability to write clear and concise code Experience with digital circuit simulation User knowledge of Linux Knowledge of versioning tools more »
Key Skills/Experience: Degree in Electronic Engineering or another relevant discipline ASIC Design & Implementation FPGA development Broad knowledge of Digital Design Verilog/SystemVerilog/VHDL Any mix of the following is nice to have: Xilinx FPGAs Design synthesis, static timing analysis, digital block routing etc. Cadence Virtuoso Benefits more »
Greater Bristol Area, United Kingdom Hybrid / WFH Options
IC Resources
enhancing Verification strategy and architecture of IP testbenches. Key Skills At least 8 years of experience in Verification working with Verilog and/or SystemVerilog; 5 years of experience on IP/block level Test-bench bring up on SV UVM based platform; The ability to understand complex design specification more »
help develop digital designs for custom IC integration and design and validate new silicon designs. Experience: Experience in ASIC or FPGA Design Strong Verilog, SystemVerilog experience Python experience CPU architecture is a plus. You will be part of a company where the work environment is stimulating and exciting, as you more »
to enhancing Verification strategy and architecture of IP testbenches.Key Skills At least 8 years of experience in Verification working with Verilog and/or SystemVerilog; 5 years of experience on IP/block level Test-bench bring up on SV UVM based platform; The ability to understand complex design specification more »
x2 Location: Cambridge Salary: £88k-£119k (depending on experience) What you need to be successful in this role: Experience writing Hardware description languages ideally SystemVerilog Experience using EDA simulators (Siemens, Synopsys, Cadence) Experience working with version control and code review systems (Git, Gerrit) Experience with CI (Jenkins) Scripting for design more »
help develop digital designs for custom IC integration and design and validate new silicon designs. Experience: Experience in ASIC or FPGA Design Strong Verilog, SystemVerilog experience Python experience CPU architecture is a plus.You will be part of a company where the work environment is stimulating and exciting, as you are more »
Full and deep understanding of the CPU architectures is an advantage; Expertise in hardware verification languages such as SV UVM, UVM and SVAs, and SystemVerilog; Knowledge of verification platform and framework development, RTL and Gate level (optional) functional verification; Proven experience of IP/Sub-System/SoC verification including more »
as all elements of the design flow, including simulation, synthesis, testbench development etc, working alongside the firmware and SoC teams. Requirements: Strong Verilog and SystemVerilog skills for RTL development Minimum 5 years of experience with the full IC design flow, including Simulation, synthesis, timing closures, placement, routing, linting etc. Experience more »
gadgets on the market today and in the future. The ideal candidate will have: Proven experience of digital ASIC verification techniques Strong experience in SystemVerilog or Verilog testbench creation Experience with OVM, VMM, UVM methodologies Effective problem solving, communication and team working skills (essential!) This position offers the opportunity to more »
years of experience in silicon verification, with a strong focus on processor verification especially using instruction set simulators is desired. Verification Expertise: Proficiency in SystemVerilog and C/C++ or Python for designing and implementing testbenches, and test cases for processor verification. You must already be based in Europe to more »
tools. eg. Cadence, Jasper Gold, Siemens EDA QuestaFormal, or Synopsys. Keywords: Formal Verification/Semiconductor/Semi conductor/Semi-conductor/GPU/SystemVerilog/System Verilog Assertions/Property Specification Language/Cadence/JasperGold/Siemens EDA/Synopsys If you are interested in this Formal Verification more »
Microprocessor architecture (CPU) and have at least 6 years’ experience in processor verification. Experience in unit and full chip level test benches. Fluent in Systemverilog, C/C++ and Python. Knowledge of RISC-V ISA would be advantageous. Your benefits package will depend on position, but your benefits programme will more »
knowledge of CI/CD concepts and source code management tools. Due to the specialised nature of the work, additional experience or knowledge of SystemVerilog, the internal structure of ICs, and embedded firmware development will be beneficial to your application. Requirements: Strong Python development skills covering testing frameworks and object more »
