10 of 10 Tcl Jobs in the South East

61508. Familiarity with high-speed interfaces and protocols (e.g., AXI, DDR, HDMI, PCIe, USB, Ethernet). Scripting skills in TCL or Python for build automation or verification support. Exposure to model-based design workflows (e.g., MATLAB/Simulink integration). ...

highly utilised designs and clock domain crossing (CDC). Toolchains: Deep experience with design and verification tools such as Xilinx Vivado, Vitis, and TCL scripting. Lab/debug skills: Familiarity with hardware debugging tools, such as JTAG debuggers, oscilloscopes, spectrum analysers, signal generators, and logic analysers, and lab bring ...

experience Knowledge of FPGA toolchains (Vivado, Quartus, ModelSim) Experience with SoC devices (e.g. Zynq UltraScale+) Desirable: Video/RF protocols (MIPI, SDI) Python or TCL scripting High-reliability, defence, or aerospace experience UK Security Clearance (SC or DV) This FPGA Engineer job offers the chance to develop in a very ...

Knowledge of FPGA toolchains (Vivado, Quartus, ModelSim)li> Experience with SoC devices (e.g. Zynq UltraScale+) Desirable: Video/RF protocols (MIPI, SDI) Python or TCL scripting High-reliability, defence, or aerospace experience UK Security Clearance (SC or DV) This FPGA Engineer job offers the chance to develop in a very ...

experience. Good understanding of RTL design principles and hardware implementation. Experience with coverage-driven and assertion-based verification. Linux proficiency with Python, Tcl or Bash scripting skills. Strong analytical, debugging and problem-solving skills. Experience using AI to accelerate verification while maintaining quality. Ability to collaborate effectively across multiple engineering ...

accurate modelling techniques Strong understanding of timing closure, clock domain crossing (CDC) and advanced digital design principles Experience with Xilinx Vivado, Vitis and TCL scripting toolchains Familiarity with hardware debugging tools including oscilloscopes, logic analysers, JTAG debuggers and signal generators This is an opportunity to work at the forefront ...

accurate modelling techniques Strong understanding of timing closure, clock domain crossing (CDC) and advanced digital design principles Experience with Xilinx Vivado, Vitis and TCL scripting toolchains Familiarity with hardware debugging tools including oscilloscopes, logic analysers, JTAG debuggers and signal generators This is an opportunity to work at the forefront ...

skills. Understanding of RTL design principles and hardware implementation. Experience with coverage-driven and assertion-based verification. Linux proficiency and scripting skills (Python, Tcl or Bash). Strong analytical, debugging and problem-solving skills. Experience using AI to accelerate verification without sacrificing quality Ability to work across multiple teams Desirable ...

aligned to engineering best practice. Take ownership of simulation, synthesis, timing closure, hardware validation and design optimisation. Drive effective use of Linux‐based toolchains, TCL/IP‐core flows and build automation to support rapid, repeatable development. Support system integration and cross‐functional collaboration with hardware, software, systems and test ...

timing concepts, and digital architectures Exposure to Verilog, SystemVerilog, or VHDL through academic projects, placements, internships, or personal projects Basic knowledge of Python, MATLAB, Tcl, or Bash Strong analytical, problem-solving, and debugging skills Ability to communicate technical concepts clearly through written reports and verbal presentations Structured approach to engineering … Digital Hardware Design RTL Design Using SystemVerilog FPGA Development Testbench Development Wireless Communication Technologies ATS Optimization Keywords Hard Skills SystemVerilog Verilog VHDL Python MATLAB Tcl Bash Digital Signal Processing FPGA ASIC Soft Skills Analytical Skills Problem-Solving Communication Skills Attention to Detail Team Collaboration Industry Keywords Wireless Communication ...