16 of 16 Tcl Jobs in the South East

Vitis, Quartus, Libero, Diamond, Radiant, Precision or Propel. Verification methodologies: OSVVM, UVVM or UVM. Simulation tools: Siemens ModelSim/QuestaSim or AMD XSim. Scripting: TCL and/or Python. Requirements management: IBM Rational DOORS or Siemens Polarion. Interface and protocol knowledge: PCIe, Ethernet, serial communications, AXI4, OCP, Wishbone, JESD204, CameraLink ...

experience Knowledge of FPGA toolchains (Vivado, Quartus, ModelSim) Experience with SoC devices (e.g. Zynq UltraScale+) Desirable: Video/RF protocols (MIPI, SDI) Python or TCL scripting High-reliability, defence, or aerospace experience UK Security Clearance (SC or DV) This FPGA Engineer job offers the chance to develop in a very ...

toolchains (Vivado/Questa). Hands-on experience with high-speed interfaces (PCIe/DMA) and lab debugging tools. Scripting for workflow automation (Python, Tcl, Make). Degree in Electronic Engineering or equivalent industry background. Apply: Interested in leading core architecture on high-impact technology? Apply with your CV today ...

design reviews, testing and documentation throughout the development lifecycle. Essential Skills & Experience Strong FPGA development experience across major FPGA families. Proficiency with Xilinx tools, TCL, Verilog, SystemVerilog and UVM. Experience with Xilinx 7 Series, UltraScale, Intel (Altera) or Microsemi FPGA architectures. Knowledge of high-speed interfaces such as PCIe, Ethernet ...

accurate modelling techniques Strong understanding of timing closure, clock domain crossing (CDC) and advanced digital design principles Experience with Xilinx Vivado, Vitis and TCL scripting toolchains Familiarity with hardware debugging tools including oscilloscopes, logic analysers, JTAG debuggers and signal generators This is an opportunity to work at the forefront ...

highly utilised designs and clock domain crossing (CDC). Toolchains: Deep experience with design and verification tools such as Xilinx Vivado, Vitis, and TCL scripting. Lab/debug skills: Familiarity with hardware debugging tools, such as JTAG debuggers, oscilloscopes, spectrum analysers, signal generators, and logic analysers, and lab bring ...

fault-investigation skills. The ability to analyse failures and work with design engineers to identify their underlying causes. Experience automating test execution using Python, Tcl , Bash or a similar scripting language. Experience using Git, Subversion or another revision-control system. The ability to produce clear technical documentation covering verification architecture ...

topics (e.g. FOC, PWM generation, encoders/resolvers, current/torque loops, or real-time motion control on FPGA) is a plus Scripting experience (Tcl, Python, and/or Perl) for automation of build, simulation, and timing flows Familiarity with Avalon and/or AXI protocols, low-level HAL/ ...

aligned to engineering best practice. Take ownership of simulation, synthesis, timing closure, hardware validation and design optimisation. Drive effective use of Linux‐based toolchains, TCL/IP‐core flows and build automation to support rapid, repeatable development. Support system integration and cross‐functional collaboration with hardware, software, systems and test ...

architecture and verification Experience with tools such as Vivado, Quartus, ModelSim or QuestaSim Experience with SoC platforms, high-speed interfaces, DSP, MATLAB, Python/Tcl, MBSE or safety-critical systems would be advantageous. We’re also open to engineers from a variety of technical backgrounds, including defence, aerospace, automotive, communications ...

lateral-thinking approach to problem solving Preferred Skills and Qualifications Experience with formal verification and verification qualification techniques Scripting experience: Ruby, sh/csh, TCL, Make, Perl Power-aware verification (using CPF/UPF) Object-oriented programming and use of OOP design patterns Additional Information Hybrid remote position: 2+ days ...

photonics platforms Experience with optical/photonic simulation tools (e.g., FDTD, mode solvers, circuit-level simulators) Familiarity with foundry PDK-based photonic design flows Tcl scripting #J-18808-Ljbffr ...

flows against foundry PDKs and help ensure clean tapeouts. You''ll collaborate with design, layout, and CAD teams, build automation tools in Python/Tcl/shell, and maintain verification libraries under version control to support scalable, repeatable processes. #J-18808-Ljbffr ...

verification experience, proficiency with Calibre or Synopsys ICV for DRC/LVS signoff, GDS/OASIS knowledge, and strong scripting skills in Python/Tcl/Shell. #J-18808-Ljbffr ...

tracing defects to their underlying causes. Using simulation, synthesis and hardware-debugging tools. Automating engineering tasks using scripting languages such as Python or Tcl . Taking part in design and code reviews. Communicating technical progress, decisions and results clearly to colleagues. Learning and applying the quality and safety standards required … Vivado or Altera Quartus Prime. Familiarity with testbenches or verification concepts. Experience using simulation tools such as QuestaSim . Exposure to Python, Tcl or another scripting language. Familiarity with Git, Subversion or another revision-control system. University, personal or commercial projects involving FPGA development, embedded systems, digital signal processing, communications ...

device recognition issues Read, manipulate, and QA GDS/OASIS layout data Maintain and extend verification runsets and rule decks Build Python/Tcl/shell tooling to automate verification flows and triage error reports Maintain verification libraries and runsets under version control, with controlled release processes Handle third-party … Cadence Virtuoso or Synopsys CustomCompiler Strong working knowledge of GDS/OASIS formats and LVS concepts Proficiency with Linux and scripting in Python, Tcl, or shell Experience managing rule decks, runsets, or libraries under version control (e.g., Git) Ability to independently debug complex hierarchical netlist and layout issues Strong written ...