8 UVM Jobs in the South East

Generating complex FPGA architectures and design implementations (VHDL, Simulink etc), targeting Xilinx, Intel, Microsemi devices. Verifying complex FPGA implementations using VHDL and System Verilog\UVM test-bench methodologies. Using FPGA design toolsets and Mentor verification tools (QuestaSim & ModelSim). Generating low-level software (C) to facilitate FPGA test and integration more »

Generating complex FPGA architectures and design implementations (VHDL, Simulink etc), targeting Xilinx, Intel, Microsemi devices. Verifying complex FPGA implementations using VHDL and System Verilog\UVM test-bench methodologies. Using FPGA design toolsets and Mentor verification tools (QuestaSim & ModelSim). Generating low-level software (C) to facilitate FPGA test and integration more »

facilities to deliver Firmware for complex digital systems that meet challenging future customer requirements. • Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM • FPGA architectures such as Xilinx 7. Xilinx UltraScale Intel (Altera) or Microsemi (Actel) • Fast interfaces such as PCIe, Ethernet, and JESD is also required • Auto more »

Metric driven verification - verification planning, requirements extraction - Directed and constrained random verification - Functional and code coverage analysis SystemVerilog Testbench design with verification frameworks like UVM/OVM, e, VMM Debugging skills - RTL - Testbench, OOP - Gate level (including SDF) Formal verification and verification qualification techniques Scripting experience with Ruby, sh/ more »

include: A Bachelors or Masters Degree in an Electronics related discipline. Proven experience working within the Semiconductor industry. Competence in Digital Design Verification using UVM or similar. Experience with SystemVerilog Assertions. Good knowledge of simulation tools (Cadence ideal). A track record in verifying complex designs. Good Scripting skills. The more »

over 40 years’ experience, as they look to expand their Verification team. Bachelors or Masters in Electronic Engineering or a related field Experience with UVM/OVM Experience with System Verilog and System Verilog Assertions Strong Debugging skills For more information on this role or others then please contact Jordan more »

PhD (desirable) 12+ years of digital ASIC verification experience Practical experience and understanding of: Requirement capture, verification planning and coverage closure System Verilog and UVM test benches Creation of UVM test benches System Verilog assertions Managing regression and debugging failures Scripting languages (e.g. Perl/Python/TCL) As this more »

PhD (desirable) 12+ years of digital ASIC verification experience Practical experience and understanding of:Requirement capture, verification planning and coverage closure System Verilog and UVM test benches Creation of UVM test benches System Verilog assertions Managing regression and debugging failures Scripting languages (e.g. Perl/Python/TCL) As this more »