Junior to Mid-Level FPGA Design Engineer
Leicester, England, United Kingdom
Express Recruitment
UKAS) ISO 17025 and standard calibration Qualifications & Experience Experience in some form of FPGA design required Exposure to RTL design and coding experience with VHDL (or Verilog) Knowledge of CPU or DSP architectures advantageous Ability to learn how to develop large Altera and Xilinx FPGAs using VHDL (or Verilog) Experience more ยป
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