Verification Engineer Jobs in Cambridgeshire

2 of 2 Verification Engineer Jobs in Cambridgeshire

Senior Design Verification Engineer

Cambridge, England, United Kingdom
Mulya Technologies
Senior Design Verification Engineer Cambridge,/Bristol England, United Kingdom Our client can be described as "Developing Foundational Technologies for Chiplet Based Semiconductor Design". They are an early-stage startup, pioneering technologies for the emerging multi-chiplet system-on-package paradigm. Their mission is to enable the next wave of growth in the semiconductor space, and they … re looking for passionate individuals to join a seasoned and dynamic team. Senior D esign Verification engineer Responsibilities: Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define … Preferred Skills BS, MS in Electrical Engineering, Computer Engineering or Computer Science 8-12 years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based test benches Experience with modern programming languages like Python Knowledge More ❯
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Senior Design Verification Engineer

cambridge, east anglia, united kingdom
Mulya Technologies
Senior Design Verification Engineer Cambridge,/Bristol England, United Kingdom Our client can be described as "Developing Foundational Technologies for Chiplet Based Semiconductor Design". They are an early-stage startup, pioneering technologies for the emerging multi-chiplet system-on-package paradigm. Their mission is to enable the next wave of growth in the semiconductor space, and they … re looking for passionate individuals to join a seasoned and dynamic team. Senior D esign Verification engineer Responsibilities: Create test plans for highly configurable IPs meant to provide interconnectivity between components across an SoC, chiplet, or multi-chiplet systems Write UVM/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define … Preferred Skills BS, MS in Electrical Engineering, Computer Engineering or Computer Science 8-12 years and current hands-on experience in block-level/IP-level/SoC-level verification Proficiency in Verilog, SystemVerilog Familiarity with industry-standard EDA tools for simulation and debug Deep experience with UVM-based test benches Experience with modern programming languages like Python Knowledge More ❯
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