Permanent Verilog Jobs in the Thames Valley

1 to 4 of 4 Permanent Verilog Jobs in the Thames Valley

Principal FPGA Engineer

Milton Keynes, England, United Kingdom
Belcan
Industry or university research experience in the design, analysis, and implementation of FPGA systems at the HDL level. Expertise in FPGA design and verification (Verilog/VHDL, HDL coder, Xilinx's Vivado, Modelsim, etc.). Hands-on experience with lab instruments such as digital oscilloscopes, spectrum analyzers, RF signal generators more »
Posted:

Senior FPGA Development Engineer

Slough, Berkshire, South East, United Kingdom
Redline Group Ltd
related discipline - Knowledge of 4G or 5G standards - A deep understanding of FPGA fabric and clocking resources is essential. - Proficiency in hardware programming languages (Verilog and/or VHDL) is essential - Experience with RTL-level design, simulation and verification is essential - Experience with design and implementation using Avalon and/ more »
Employment Type: Permanent
Salary: £60,000
Posted:

Senior FPGA Design Engineer

Maidenhead, England, United Kingdom
Hybrid / WFH Options
Yoh, A Day & Zimmermann Company
bonus, share options, 25 days holiday (plus stats), pension, life insurance, healthcare etc.. Senior FPGA Design Engineer with expertise in digital design using Verilog, Vivado, and ModelSim required by innovative, international 5G solutions provider. The Senior FPGA Engineer will play an important role as an individual contributor within an international … IC Design (FPGA/ASIC) expertise from architecture through to design and verification Strong skills in front end RTL design of Xilinx FPGAs using Verilog and Vivado Strong skills in simulation tools (eg. QuestaSim and/or ModelSim) Skills in hardware debugging Strong communication skills, able to work effectively as more »
Posted:

Design Verification Engineer

Oxfordshire, England, United Kingdom
Hybrid / WFH Options
IC Resources
related field. PhD (desirable) 12+ years of digital ASIC verification experience Practical experience and understanding of: Requirement capture, verification planning and coverage closure System Verilog and UVM test benches Creation of UVM test benches System Verilog assertions Managing regression and debugging failures Scripting languages (e.g. Perl/Python/TCL more »
Posted:
Verilog
the Thames Valley
25th Percentile
£52,250
Median
£56,500
75th Percentile
£85,000