Senior Design Engineer
Ely, England, United Kingdom
Circle Group
Verilog/VHDL experience 5+ years FPGA (Quantus, Vivado, Altera) experience Bachelors and Masters/PhD in Mathematics, Engineering (Or Similar) Experience with C++, C or python coding languages Familiar with Linux operating systems Benefits Starting salary between £65,000 - £85,000 per annum 25 days holiday plus Bank Holidays more »
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