4 of 4 Remote/Hybrid SystemVerilog Jobs in London

based verification at IP and subsystem levels Proven experience building UVM testbenches from scratch Proficiency in Python for verification automation Solid experience with SystemVerilog Assertions (SVA) A minimum of 4 years experience. What’s on offer Competitive base salary plus share options Opportunity to help build something from the ground ...

responsible for defining, implementing, and optimising RTL-level digital logic for complex ASIC and SoC designs. Key Responsibilities Translate architectural specifications into efficient, synthesizable SystemVerilog RTL. Develop detailed micro-architecture specifications for functional blocks and subsystems. Integrate IP blocks and ensure robust connectivity and data flow across the SoC. Requirements … Electrical Engineering, Computer Engineering, or a related discipline. 3+ years’ experience in digital logic/RTL design for ASIC or SoC projects. Strong SystemVerilog skills. Solid understanding of digital design fundamentals. Experience using EDA tools for simulation, synthesis, and linting. Familiarity with low-power design techniques, timing analysis, and common ...

Ensure the functional correctness and performance of complex digital ASIC Core/IP designs, including deep unit and core-level verification. Develop robust SystemVerilog/UVM verification environments. Create and execute tests to achieve high coverage and debug complex failures. Collaborate closely with design teams to deliver high-quality results. … Automate verification flows using Python or Perl scripts. What Were Looking For: 7+ years of hands-on experience in digital verification. Expertise in SystemVerilog/UVM and strong digital design knowledge. Experience verifying digital systems using standard IP components (e.g., microprocessor cores, hierarchical memory subsystems). Proficiency with EDA simulation ...

with quarterly visits to London. What You’ll Do Own unit‐level and core‐level verification for complex digital IP Build scalable SystemVerilog/UVM environments Develop constrained‐random and directed tests to drive high coverage Debug failures across RTL, testbench, and micro‐architecture Automate regressions and flows using Python … with modern IP ecosystems: microprocessor cores, memory subsystems, AMBA interconnects, system debug logic What You Bring 3–4+ years of digital verification experience Strong SystemVerilog/UVM expertise Solid understanding of digital logic and verification methodologies Experience with ARM‐based components (M‐class cores, NIC, Coresight, AMBA protocols) Familiarity with ...