3 of 3 Remote/Hybrid SystemVerilog Jobs in London

based verification at IP and subsystem levels Proven experience building UVM testbenches from scratch Proficiency in Python for verification automation Solid experience with SystemVerilog Assertions (SVA) A minimum of 4 years experience. What’s on offer Competitive base salary plus share options Opportunity to help build something from the ground ...

chiplet-based designs featuring multi-processors and high-speed I/Os, working closely with RTL and DV teams. Key Responsibilities Develop and optimize SystemVerilog Assertions (SVA) and formal properties Perform formal verification at block, subsystem, and full-chip levels Create abstractions, assumptions, and constraints for proofs Identify bugs, dead … teams to achieve verification coverage closure Required Qualifications BSc or MSc in EE, CE, CS, Mathematics, or Physics Strong knowledge of SystemVerilog/Verilog and digital design Hands-on experience with formal verification methodologies Proficiency with SVA (PSL a plus) Experience with at least one formal tool ( JasperGold, VC Formal ...

Ensure the functional correctness and performance of complex digital ASIC Core/IP designs, including deep unit and core-level verification. Develop robust SystemVerilog/UVM verification environments. Create and execute tests to achieve high coverage and debug complex failures. Collaborate closely with design teams to deliver high-quality results. … Automate verification flows using Python or Perl scripts. What Were Looking For: 7+ years of hands-on experience in digital verification. Expertise in SystemVerilog/UVM and strong digital design knowledge. Experience verifying digital systems using standard IP components (e.g., microprocessor cores, hierarchical memory subsystems). Proficiency with EDA simulation ...