Senior / Staff Digital Design Engineer
London, England, United Kingdom
Flux Computing
real‐time data stream. Proven success closing timing on multi‐hundred‐MHz to multi‐GHz clock domains and integrating high‐speed IP (e.g., SerDes, HBM/DDR, PCIe, 100 GbE or similar). Expertise with industry‐standard EDA flows: RTL synthesis, CDC/RDC, STA, power‐intent (UPF/CPF), lint, and gate‐level simulation. Demonstrated FPGA prototyping skills: constraint More ❯
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