Cambridge, Cambridgeshire, East Anglia, United Kingdom
Langham Recruitment Limited
SVA, VIP, and UPF), for ASIC implementation. Strong RTL coding with Verilog and System Verilog. Strong knowledge of interface technology (I2C, SPI, UART, SWD, JTAG, etc). Strong knowledge of on-chip bus protocol (AMBA AHB, APB, AXI-Stream, etc). Experience with Linux OS, revision control (Git) and scripting more »
write testbenches for simulationGood knowledge of clock and reset scheme and power domain structureGood knowledge of industry-standard interface technology (I2C, SPI, UART, SWD, JTAG, etc)Good knowledge of on-chip bus protocol (AMBA AHB, APB, AXI-Stream, etc)Experience in digital IC design backend flow synthesis, STA, test insertion more »
verification (UVM, SVA, VIP, and UPF), for ASIC implementation.Strong RTL coding with Verilog and System Verilog.Strong knowledge of interface technology (I2C, SPI, UART, SWD, JTAG, etc).Strong knowledge of on-chip bus protocol (AMBA AHB, APB, AXI-Stream, etc).Experience with Linux OS, revision control (Git) and scripting languages (Bash more »
Module or TestMax)Analytical thinking and attention to detailHighly skilled individual with many successful tape outs/experienceMBIST expertATPG/scan insertion expertScan compression, JTAG, OCCVery good vector generation and simulation skillsIndustry knowledge of ATE test systems like Teradyne or AdvantestWhy apply for this job ?You will have the opportunity more »
SVA, VIP, and UPF), for ASIC implementation. Strong RTL coding with Verilog and System Verilog. Strong knowledge of interface technology (I2C, SPI, UART, SWD, JTAG, etc). Strong knowledge of on-chip bus protocol (AMBA AHB, APB, AXI-Stream, etc). Experience with Linux OS, revision control (Git) and scripting more »
thinking and attention to detail Highly skilled individual with many successful tape outs/experience MBIST expert ATPG/scan insertion expert Scan compression, JTAG, OCC Very good vector generation and simulation skills Industry knowledge of ATE test systems like Teradyne or Advantest Why apply for this job ? You will more »
for simulation Good knowledge of clock and reset scheme and power domain structure Good knowledge of industry-standard interface technology (I2C, SPI, UART, SWD, JTAG, etc) Good knowledge of on-chip bus protocol (AMBA AHB, APB, AXI-Stream, etc) Experience in digital IC design backend flow synthesis, STA, test insertion more »
several successful ASIC projects. Implementing DFT infrastructure. Experience generating and debugging Scan ATPG patterns. Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, and MBIST.If you are interested in finding out more, or applying for this position, please contact Lucy Edmondson at IC Resources more »
