Farnborough, Hampshire, South East, United Kingdom
Hays
testing. Hierarchical/Flatten Flow: Experience managing hierarchical and flatten design representations. ATPG Generation: Skill in generating Automatic Test Pattern Generation (ATPG) patterns. SDC (Synopsys Design Constraints) Support: Provide full SDC support for the physical team, ensuring seamless timing closure from synthesis to full-chip flatten Static Timing Analysis (STA more »
Desirable/Optional) Working with version control and project management/bug tracking systems such as SVN/Git and Jira. Xilinx FPGA technology. Synopsys tool flows. Experience using Arm DS5/DSTREAM debugger (Desirable/Optional) Excellent written and spoken English; can write coherent documentation more »
synthesis, STA, test insertion, MBIST, formality, GDS layout etc Experience in EDA tools for custom IC development like Siemens Questa for simulation and verification, Synopsys DesignCompiler for synthesis and STA, Spyglass for linting, etc. Experience in writing IP design specifications and block level modules Good knowledge of UVM, SVA, VIP more »
at wafer- and package-level; A good understanding of statistical analysis and design of experiments; Knowledge of semiconductor TCAD tools for device simulation, i.e. Synopsys Sentaurus, Silvaco Victory; Background in electronics engineering for system understanding in the field of power electronics. Excellent problem-solving skills – able to identify problems and more »
design, computer architecture, and semiconductor device physics Familiarity with neuromorphic algorithms and computational models Experience with industry-standard EDA tools (e.g., Vivado or Cadence, Synopsys, or Mentor Graphics) Strong problem-solving skills and the ability to work independently and collaboratively Excellent communication and interpersonal skills Nice-to-have: Publications or more »
conductor/Semi-conductor/GPU/SystemVerilog/System Verilog Assertions/Property Specification Language/Cadence/JasperGold/Siemens EDA/Synopsys If you are interested in this Formal Verification Engineer position, please send a CV to ts@eu-recruit.com By applying to this role you understand more »
Cambridge, England, United Kingdom Hybrid / WFH Options
Connected Consulting Limited
e.g. C++) Experience with the implementation of ASIC/SoC RTL in FPGA SV UVM test benches, using UVM Verification IPs Xilinx FPGA technology. Synopsys tool flows. If you have the required experience and want to be part of a team that helps build innovative products that impact millions of more »
Farnborough, Hampshire, South East, United Kingdom
Hays
Practical use of scripting languages Tcl/Python/Perl etc Experience of at least one of the following EDA tool flows: Cadence or Synopsys Communicating with other design teams, 3rd party IP and library suppliers and EDA tool vendors to improve scripts and tool flow Managing/Interfacing to more »
