Permanent Synopsys Jobs in the UK excluding London

6 Permanent Synopsys Jobs in the UK excluding London

System Verification Engineer

Cambridge, England, United Kingdom
Arm
Desirable/Optional) Working with version control and project management/bug tracking systems such as SVN/Git and Jira. Xilinx FPGA technology. Synopsys tool flows. Experience using Arm DS5/DSTREAM debugger (Desirable/Optional) Excellent written and spoken English; can write coherent documentation more »
Posted:

Senior Design Verification Engineer

Cambridge, England, United Kingdom
Hybrid / WFH Options
Connected Consulting Limited
e.g. C++) Experience with the implementation of ASIC/SoC RTL in FPGA SV UVM test benches, using UVM Verification IPs Xilinx FPGA technology. Synopsys tool flows. If you have the required experience and want to be part of a team that helps build innovative products that impact millions of more »
Posted:

Senior Physical Design Engineer

Farnborough, Hampshire, South East, United Kingdom
Hays
Practical use of scripting languages Tcl/Python/Perl etc Experience of at least one of the following EDA tool flows: Cadence or Synopsys Communicating with other design teams, 3rd party IP and library suppliers and EDA tool vendors to improve scripts and tool flow Managing/Interfacing to more »
Employment Type: Permanent
Salary: £80,000
Posted:

Digital IC Design Engineer (RTL/ASIC)

Cambridge, England, United Kingdom
Cambridge Mechatronics Ltd
synthesis, STA, test insertion, MBIST, formality, GDS layout etc Experience in EDA tools for custom IC development like Siemens Questa for simulation and verification, Synopsys DesignCompiler for synthesis and STA, Spyglass for linting, etc. Experience in writing IP design specifications and block level modules Good knowledge of UVM, SVA, VIP more »
Posted:

DFT Engineer

Farnborough, Hampshire, South East, United Kingdom
Hays
testing. Hierarchical/Flatten Flow: Experience managing hierarchical and flatten design representations. ATPG Generation: Skill in generating Automatic Test Pattern Generation (ATPG) patterns. SDC (Synopsys Design Constraints) Support: Provide full SDC support for the physical team, ensuring seamless timing closure from synthesis to full-chip flatten Static Timing Analysis (STA more »
Employment Type: Permanent
Posted:

Formal Verification Engineer

Cambridge, England, United Kingdom
European Recruitment
conductor/Semi-conductor/GPU/SystemVerilog/System Verilog Assertions/Property Specification Language/Cadence/JasperGold/Siemens EDA/Synopsys If you are interested in this Formal Verification Engineer position, please send a CV to ts@eu-recruit.com By applying to this role you understand more »
Posted:
Synopsys
the UK excluding London
25th Percentile
£90,000
Median
£100,000
75th Percentile
£110,000