Using FPGA technologies especially from either Xilinx, Microsemi (Actel) or Lattice and their tools * Advanced verification techniques using either VHDL or System Verilog/UVM * Specifying complex timing and area constraints for efficient FPGA place and route * Ability to analyse system level requirements and derive detailed Firmware requirements * A methodical more »
facilities to deliver Firmware for complex digital systems that meet challenging future customer requirements. • Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM • FPGA architectures such as Xilinx 7. Xilinx UltraScale Intel (Altera) or Microsemi (Actel) • Fast interfaces such as PCIe, Ethernet, and JESD is also required • Auto more »
design for FPGA using VHDL Knowledge of video processing and control law algorithms Working to DO-254 Working knowledge and experience of UVM (UniversalVerificationMethodology) constrained random verificationmore »
globally. Description: Have you ever built out FPGA verification infrastructure from scratch/Processes? They need an RTL verification expert to build up a UVM system and implement RTL simulations for system-level functional verification of our FPGA designs. Ideally, this candidate would be proficient with Cadence Xcellium, as this … is the tool they use. Skills: RTL VerificationUVM FPGA Job Title: Design Verification Engineer Location: London, UK Job Type: Contract Trading as TEKsystems. Allegis Group Limited, Bracknell, RG12 1RT, United Kingdom. No Allegis Group Limited operates as an Employment Business and Employment Agency as set out in the Conduct more »