3 Verification Engineer Jobs in Cambridge with Remote Work Options

FPGA/Embedded System Engineer We think you'll love this opportunity, even if we are slightly biased! As an experienced Design & Verification Engineer Engineer, you will be part of the hardware platform team that builds development platforms for leading CPU and System IP products, that … ability to apply your RTL design skills using SystemVerilog for FPGA and/or ASIC, together with an understanding of FPGA device architecture. For verification you will be using System-Verilog and possibly UVM, this will include coding System Verilog Assertions (SVA) checks, cover-properties, SV coverage groups etc. … Tcl, Make, bash etc will also be required.. Required Skills and Experience: Proven experience of delivering RTL designs in a SoC or FPGA. RTL Verification at both unit and system level, using SV including SVA. Experience of ASIC or FPGA synthesis tools. Unix/Linux skills including shell programming more »

Verification Engineer - System Verilog/UVM - Video IP One of Orbis's clients based in Cambridge is looking for multiple Verification Engineers with experience working on Video IP & System Verilog/UVM. Ideally, you would be required to be in the Cambridge HQ 2 - 3 days p … is low coverage Contract: Start date July 1st 2024 £500 - £600 p/day Inside IR35 DoE Hybrid working 6 month contract - extensions likely Verification Engineer - System Verilog/UVM - Video IP more »

Freelance Design & Verification (FPGA) Engineer – Cambridge (England) –12 Months+ We're looking for an expert Design & Verification Engineer to join the Platform team on a contract basis. We work at the forefront of embedded IP and system design. We build physical hardware development platforms, to FPGA … accurate modelling of incoming designs, we must constantly develop new and innovative prototyping techniques. Responsibilities: of FPGA architecture specifications into RTL designs with accompanying verification environments to ensure the specifications are followed. Your designs will then be incorporated into SoC and reference designs before being thoroughly tested as system … System-)Verilog for either/or FPGA and ASIC, as well as a good understanding of FPGA device architecture is essential. role also requires verification experience using System-Verilog and possibly UVM environments including coding System Verilog Assertions (SVA) checks, cover-properties, SV coverage groups. will work with a more »