5 of 5 ASIC Engineer Jobs in the South West

ASIC Design Engineer – Wi-Fi Products Location: Bristol Type: Permanent/Full-Time Salary: Competitive + Bonus + Benefits Industry: Semiconductors/Wireless Technology About the Company Join a world-leading technology company at the forefront of wireless innovation. As an ASIC Engineer, you will work … in a collaborative environment where innovation, technical excellence, and personal development are genuinely valued. The Role I am seeking a highly skilled and motivated ASIC Engineer to join the Wi-Fi development team. In this role, you’ll contribute to the design and development of next-generation Wi …/debug if required Requirements Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field 5+ years of hands-on ASIC design experience Strong RTL design skills using Verilog or SystemVerilog Experience in SoC development and integration Familiarity with Wi-Fi, wireless MAC/PHY More ❯

ASIC Design Engineer 2-5 years Bristol I am seeking an ASIC Design Engineer to join a team of experts passionate about digital design! This role would be best suite someone embarking on the next stage and possibly second role in industry although all applicants within … the salary range and level are welcome to apply! As an ASIC Design Engineer, you will develop and enhance digital products and modules including concept and circuit design as well as physical implementation and functional validation. Role: Design Micro-Architecture from Architectural Specification and Requirements Generate complex Digital More ❯

Principal Digital Design Engineer Bristol – Cambridge, Oxford can also be considered Salary range - £80k to £100k depending on experience + RSUs + bonus Due to growth, I am looking for a Principal Digital Design Engineer with several years’ experience in industry working on ASIC developments and IP … design of both individual blocks and integration layers. You will be responsible for full-flow ownership from digital specification through to RTL for complex ASIC blocks or full-chip designs. Experience Extensive experience in integrated circuit development with a strong understanding of all stages of ASIC design, from … specification to RTL, along with a working knowledge of the RTL to tape-out process Proven expertise in ASIC microarchitecture, including interconnect design, CPU integration, DDR, PCIe, JESD204, and system-level considerations such as pinout, ballout, die size, and power consumption. Familiarity with system-on-chip interconnect protocols such More ❯

Social network you want to login/join with: Application Specific Integrated Circuit Design Engineer, bath col-narrow-left Client: IC Resources Location: bath, United Kingdom Job Category: Other - EU work permit required: Yes col-narrow-right Job Views: 2 Posted: 31.05.2025 Expiry Date: 15.07.2025 col-wide Job Description … Bristol or Oxford – 3 days onsite An exciting opportunity has arisen for a Senior Digital Design engineer to make the next step in their career and join an industry leading company designing ASICs for customers ranging from start-ups to blue chip companies, in industries including automotive, medical, space … and mobile technology companies. To be considered you must have around 10 years’ experience in industry working on ASIC developments and IP design, with at least one successful project as Technical Lead. Part of the role includes Take full-flow ownership of all stages of the digital specification to More ❯

Senior/Principal Digital Design Engineer Swindon I am seeking a Senior or Principal Digital Engineer to join a leading design centre that develops integrated circuits and MEMS solutions for a wide range of applications, working closely with customers to take designs from specification through to qualified silicon. … The engineering team is multidisciplinary, pushing the bounds of their experience to deliver each new project. Reporting to the ASIC Design Manager, the Senior/Principal Digital Design Engineer will be responsible for technical leadership, high-level simulation, and block-level design of mixed-signal ASICs. The ideal More ❯