10 of 10 ASIC Jobs in East Anglia

ASIC Design Engineer Cambridge Senior OR Principal Engineering level I am seeking an experienced ASIC Design Engineer to join an innovative HW team. The work of the whole ASIC team includes Architecture, considering software/hardware trade-offs, RTL design, Verification at block and system level, FPGA platforms for software development and extended verification as well as implementation including DFT … synthesis, place and route, timing closure, and sign-off checks. Due to growth, the company are expanding and seeking an ASIC Design Engineer to join an already talented group of Engineers. They are looking to expand the team in Cambridge with this role and are seeking an Engineer with working autonomously. Responsibilities Design, IP integration, and verification planning and execution. More ❯

ASIC Design LEAD Cambridge Global Semiconductor leader – 5 days onsite Salary + Bonus + RSUs I am seeking an ASIC Design Lead to join a leading player in Cambridge. You will have a deep understanding of digital design and a proven track record in leading teams to deliver high-quality designs and meet product schedules. This role demands exceptional technical More ❯

ASIC Design LEAD Cambridge Global Semiconductor leader – 5 days onsite Salary + Bonus + RSUs I am seeking an ASIC Design Lead to join a leading player in Cambridge. You will have a deep understanding of digital design and a proven track record in leading teams to deliver high-quality designs and meet product schedules. This role demands exceptional technical More ❯

We're building a revolutionary RISC-V-based GPU and AI platform and are looking for bright, motivated graduates to join our team. If you're passionate about digital hardware design, want to learn from experienced engineers, and are excited More ❯

We're building a revolutionary RISC-V-based GPU and AI platform and are looking for bright, motivated graduates to join our team. If you're passionate about digital hardware design, want to learn from experienced engineers, and are excited More ❯

Master's degree in Electrical Engineering, Computer Engineering, or a related field Strong understanding of hardware verification methodologies and tools Experience with UVM (Universal Verification Methodology) for FPGA/ASIC verification Familiarity with security features and protocols, such as CHERI, is a plus Excellent communication skills and the ability to work effectively in a collaborative, multidisciplinary team Day-to-day More ❯

About the company: We are seeking an experienced ASIC Design Lead, to take ownership of IP and SoC-level design for next-generation semiconductor designs. This role offers the chance to lead a small team, shape verification strategy, and contribute to cutting-edge projects in a fast-paced, collaborative environment. About the role: As the ASIC Design Lead, you will … role suited to someone passionate, motivated by the challenges of building something from the ground up in a start-up environment. What you will be doing: Define and execute ASIC plans for IP/SoC designs Drive functional coverage, assertions, and bug resolution Collaborate with design, architecture, and software teams Mentor junior engineers and guide verification best practices Requirements: 6+ More ❯

About the company: We are seeking an experienced ASIC Design Lead, to take ownership of IP and SoC-level design for next-generation semiconductor designs. This role offers the chance to lead a small team, shape verification strategy, and contribute to cutting-edge projects in a fast-paced, collaborative environment. About the role: As the ASIC Design Lead, you will … role suited to someone passionate, motivated by the challenges of building something from the ground up in a start-up environment. What you will be doing: Define and execute ASIC plans for IP/SoC designs Drive functional coverage, assertions, and bug resolution Collaborate with design, architecture, and software teams Mentor junior engineers and guide verification best practices Requirements: 6+ More ❯

are available until 30 September 2027. Applications are invited for a full-time Research Assistant/Associate to work on the design and implementation of next-generation AI hardware (ASIC) accelerators. The UK's Advanced Research Invention Agency (ARIA) is supporting an ambitious programme of work that aims to reduce the the cost of AI by more than 1000x: https … candidate will be able to lead the continued design and implementation of this accelerator, i.e. exploring optimisations at the architectural and microarchitectural levels and pushing the design through the ASIC/EDA tools to generate accurate estimates of performance, power and area (PPA) for inclusion in our simulator framework. Candidates will ideally have worked on complex digital hardware designs and … not particularly relevant for this role. It should be possible to take someone with extensive experience of using FPGA tools and provide them the necessary training to use the ASIC tools. The team at Cambridge consists of three investigators: Prof. Robert Mullins (PI), Prof. Timothy Jones and Dr Rika Antonova, three PhD students and a postdoctoral researcher. The project is More ❯

Senior DFT Engineer – Join a World-Class ASIC Design Team in Cambridge! Are you a seasoned DFT Engineer with a drive for innovation and a passion for silicon design? This is a rare opportunity to join a cutting-edge ASIC team based in Cambridge , renowned for its pioneering work and collaborative approach to product development. As a Senior DFT Engineer … you will work on state-of-the-art ASIC projects, influencing the full design lifecycle while advancing your technical and leadership skills in a dynamic and forward-thinking environment. Role Overview In this role, you'll take the lead in developing and implementing Design-for-Test (DFT) strategies across a wide range of silicon technologies. You’ll work alongside cross … debug simulation environments. Work with advanced EDA tools for simulation (both behavioral and gate-level) and BIST integration. Skills: Strong industry experience in DFT architecture , implementation, and verification within ASIC or SoC development flows. Hands-on expertise in scan stitching, ATPG, boundary scan, on-chip clocking , and DFT partitioning . Proficient in using modern DFT tools (e.g., Synopsys, Cadence, or More ❯