Farnborough, Hampshire, South East, United Kingdom
Hays
implementation at block and chip level Insertion of DFT test structures and chip level integration, capture, and simulation Skills needed to succeed COT/ASIC physical design flow covering: Synthesis, Floor planning, Place and Route (P&R), Clock Tree Synthesis (CTS), Parasitic Extraction, Static Timing Analysis (STA) and Timing Closure more »
Farnborough, England, United Kingdom Hybrid / WFH Options
IC Resources
several locations, so hybrid & remote working are a possibility. Key skills for this role: A strong track record in DFT gained across several successful ASIC projects. DFT experience including architecture specification, implementation, test pattern development and verification. Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, and MBIST. more »
Farnborough, Aldershot, Hampshire, South East Hybrid / WFH Options
IC Resources
several locations, so hybrid & remote working are a possibility. Key skills for this role: A strong track record in DFT gained across several successful ASIC projects. DFT experience including architecture specification, implementation, test pattern development and verification. Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, and MBIST. more »
