5 of 5 Actel Jobs in Edinburgh

Verilog an advantage but not essential. Implementing high speed, multi-frequency clocking architecturesDesign with FPGA technologies from either AMD(Xilinx), Intel (Altera) or Microsemi (Actel).Use of Xilinx Vivado or Altera Quartus II/Quartus Prime is an advantageExperience of FPGA architectures such as SoC system-on-chip (e.g. ...

Verilog. Experience with Mentor Graphics tools, including HDL Designer, ModelSim/Questa and Precision. Knowledge of Xilinx, Intel/Altera or Microsemi/Actel design flows, including ISE, Vivado and Quartus. Experience specifying timing and area constraints for FPGA place and route. Independent FPGA verification experience using VHDL. Experience ...

design verification Ensure that all firmware designs follow the company firmware process Experience using FPGA technologies from either Xilinx, Intel (Altera) or Microsemi (Actel) and their tools FPGA design and analysis Hardware requirements capture and management Production of material for design reviews Nice To Have Experience in Siemens tools ...

other disciplines Experience with Mentor Graphics tools, including HDL Designer, ModelSim/Questa and Precision Familiarity with Xilinx, Intel (Altera) and/or Microsemi (Actel) design flows, including Vivado, Quartus and ISE Experience with timing/area constraints, synthesis and Place & Route Experience with independent FPGA verification using VHDL ...

Verilog Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim/Questa and Precision Familiar with Xilinx/Intel (Altera)/Microsemi (Actel) design flows (ISE, Vivado, Quartus) and third-party synthesis toolsExperience in specifying timing and area constraints for efficient FPGA Place and Route.Independent verification using … Verilog Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim/Questa and Precision Familiar with Xilinx/Intel (Altera)/Microsemi (Actel) design flows (ISE, Vivado, Quartus) and third-party synthesis toolsExperience in specifying timing and area constraints for efficient FPGA Place and Route.Independent verification using ...