5 of 5 Cadence Jobs in Farnborough

role is based in Farnborough, UK or Sophia Antipolis, France and involves providing technical leadership across CAD strategy and mentoring engineers. You will develop Cadence flows, automate SKILL scripts, manage verification frameworks, and collaborate with foundry partners on PDK updates. #J-18808-Ljbffr ...

reduce IR drop Perform Power Integrity (PI) analysis, including IR drop , decoupling capacitor optimization , transient response analysis, and power rail validation Create schematics using Cadence OrCAD Capture , Allegro , or equivalent EDA tools Define PCB stack-up , HDI (High-Density Interconnect) technology, and multilayer PCB requirements Collaborate with … Signal Integrity (SI) principles and high-speed design methodologies Experience with PCB Stack-up , HDI Technology , and High-Layer-Count PCB Design Proficiency with Cadence OrCAD Capture , Allegro , or equivalent PCB Design Tools Experience reviewing PCB Layouts for High-Speed , Power Integrity , and RF design considerations Hands‐on experience ...

leadership, influence cross-functional CAD strategy, and serve as a subject matter expert across the organization. The tasks will include: Design, develop, and maintain Cadence-based CAD flows for RF and analogue IC design, including schematic capture, simulation, layout, and verification. Develop and maintain SKILL/SKILL++ scripts … automation to enhance designer productivity within the Cadence Virtuoso environment. Manage and support simulation frameworks using tools such as Spectre, ADE, and Maestro, including setup of corner libraries, Monte Carlo, and process variation analyses. Own and maintain physical verification flows, including LVS, DRC, PERC, and ERC, ensuring clean sign ...

leadership, influence cross-functional CAD strategy, and serve as a subject matter expert across the organization. The tasks will include:Design, develop, and maintain Cadence-based CAD flows for RF and analogue IC design, including schematic capture, simulation, layout, and verification.Develop and maintain SKILL/SKILL++ scripts and automation … enhance designer productivity within the Cadence Virtuoso environment.Manage and support simulation frameworks using tools such as Spectre, ADE, and Maestro, including setup of corner libraries, Monte Carlo, and process variation analyses.Own and maintain physical verification flows, including LVS, DRC, PERC, and ERC, ensuring clean sign-off at all stages ...

Senior Staff RF/Analogue IC CAD Engineer to lead CAD environments, design flows, and methodologies for RF and analogue ICs. You will develop Cadence-based flows, SKILL automation, manage simulation frameworks, and mentor engineers across the team; participation in design reviews and long-term CAD strategy will ...