2 of 2 Electronic Design Automation Jobs in Yorkshire

This spans system-technology co-optimisation (STCO/XTCO), front-end design automation (RTL, logic synthesis, architectural exploration, floor planning, partition-aware EDA flows), chiplet interconnect standards (UCIe, CXL, die-to-die PHY), and the open Design Commons methodology CHIMES2 is building as its core knowledge infrastructure. … specification frameworks. System-technology co-optimisation (STCO/XTCO) and mission-aware partitioning under power, thermal and security constraints. Front-end and system-level EDA for multi-die design — partition-aware synthesis, architectural exploration, system-level floor planning, cross-die timing, die-to-die interface IP. Chiplet interconnect standards ...

Advanced packaging architectures - 2.5D silicon interposer, 3D hybrid bonding, fan-out WLP/PLP, glass interposers - and their physical-design implications. Back-end EDA and physical implementation for multi-die stacks - place-and-route, cross-die DRC/LVS, packaging parasitics extraction, packaging-aware timing and signal/power … Technology landscape and roadmap Lead WP1 Activities: Direct structured landscape analyses mapping integrator needs for maturing‐TRL devices, circuits, and interposers across back‐end EDA capability, advanced packaging architectures, and manufacturing transitions. Maintain CHIMES2 Roadmaps: Develop physical implementation and manufacturing roadmaps (EDA gaps, known‐good‐die test, reliability, yield) benchmarked ...