2 of 2 Electronics Engineer Jobs in Fareham

Hardware Electronics Engineer Location: Fareham, 4 days on site per week Duration: 6 months initial Rate: up to £70 ph Umbrella Inside IR35 Position Summary Develop and implement safety critical hardware electronic solutions to meet programme requirements across the whole development lifecycle in accordance with customer requirements, legislation, human factors and business needs. Be responsible for the … test procedures using standard proprietary test equipment. • Knowledge of developing high integrity designs, preferably safety critical. • Knowledge and ability to work within hardware development lifecycle processes. • Willingness to engineer safety critical products in an industry that is highly regulated and where engineering vigour in valued. • CAS 703 Q-Pulse 4 Desirable • Knowledge using Cadence OrCAD schematic capture, Allegro More ❯

life beyond the workplace. The Role This is a very exciting opportunity for a motivated and experienced individual to thrive in a fast-paced and innovative environment. The engineer will be confident in their abilities to research and identify cutting-edge solutions for novel and challenging problems, whilst taking pride in their attention to detail and design integrity. … The role seeks an engineer with a good understanding of powertrain architectures, power distribution systems, and experience with the design and test of various power supply topologies. Familiarity in the field of wide-bandgap semiconductors like Silicon Carbide (SiC) and Gallium Nitride (GaN) is desired but not essential. All of our engineers from time to time are required … candidate will therefore show an aptitude for directing and coordinating project activities and have strong communication/interpersonal skills for working across all departments within the organisation. Create new electronics designs from first principle, through the development lifecycle to production release Power supply design AD-DC, DC-DC, Inversion Experience with one or more of the following topologies: Phase More ❯