3 of 3 Grid Computing Jobs in the City of London

Expertise in real-time messaging (e.g., AMQ), API design (JSON, Swagger), and batch processes. Infrastructure & Operations – DevOps practices, CI/CD pipelines, Git, Ansible, cloud elasticity, cost optimization, and grid computing. Delivery Approach: Deep familiarity with Agile methodologies . Capable of working autonomously or as part of a small, high-performing team. Strong analytical mindset with a proactive approach More ❯

Company Overview Flux Computing designs and manufactures optical processors to train and run inference on large AI models. Join us in London to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed. The role We are seeking a Senior Physical Layout Engineer to own the full‐custom layout of ultra … off full‐custom layouts for high‐speed analog/RF IP (TIAs, PLLs, CDRs, drivers, samplers, bias networks, ESD clamps). Drive floorplanning and top‐level integration, coordinating power‐grid, clock‐mesh, and micro‐bump/flip‐chip escape routing to meet skew and return‐loss targets. Perform parasitic extraction and EM/IR, thermal, and electro‐migration analysis … PVS/Calibre DRC‐LVS, Quantus/StarRC, Voltus/RedHawk). Deep understanding of parasitic‐aware matching, device symmetry, shielding, differential routing, guard‐ring strategy, ESD, and power‐grid design. Proven ability to optimize for sub‐pF capacitance budgets and Experience with flip‐chip, micro‐bump, 2.5D/3D IC, or chiplet integration and related challenges. Proficient in More ❯

Company Overview Flux Computing designs and manufactures optical processors to train and run inference on large AI models. Join us in London to be part of a highly motivated and skilled team that thrives on delivering impact and innovation at speed. The role We are seeking a Physical Layout Engineer to own the full‐custom layout of ultra‐high … off full‐custom layouts for high‐speed analog/RF IP (TIAs, PLLs, CDRs, drivers, samplers, bias networks, ESD clamps). Drive floorplanning and top‐level integration, coordinating power‐grid, clock‐mesh and micro‐bump/flip‐chip escape routing so 100 + channels meet skew and return‐loss targets. Perform parasitic extraction and EM/IR, thermal and … Calibre DRC‐LVS, Quantus/StarRC, Voltus/RedHawk). Deep understanding of parasitic‐aware matching, device symmetry, shielding, differential routing, guard‐ring strategy, ESD and on‐chip power‐grid design. Demonstrated ability to close sub‐pF capacitance budgets and < 5 mΩ series resistance on critical nets through careful geometry selection and EM‐aware verification. Experience with flip‐chip More ❯