10 of 10 PCIe Jobs in County Antrim

FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements. Key Skills: SystemVerilog RTL design 100Gb Ethernet, PCIe Gen5, AMBA/AXI Deep understanding of FPGA/Adaptive SoC design flow including P&R and timing closure Vivado/Vitis expertise Python/ ...

Linux, and Zephyr RTOS development Strong C/C++, Python, and bash Software flows for complex SoCs; co-simulation & hardware debug Experience with 100GbE, PCIe Proficient in Git & CI/CD Familiarity with SWs Vivado/Vitis If you are interested in this position and would like to learn more ...

FPGA/Adaptive SoC technology using SystemVerilog RTL. Deliver synthesis-ready designs meeting timing and integration requirements. Key Skills: SystemVerilog RTL design 100Gb Ethernet, PCIe Gen5, AMBA/AXI Deep understanding of FPGA/Adaptive SoC design flow including P&R and timing closure Vivado/Vitis expertise Python/ ...

Linux, and Zephyr RTOS development Strong C/C++, Python, and bash Software flows for complex SoCs; co-simulation & hardware debug Experience with 100GbE, PCIe Proficient in Git & CI/CD Familiarity with SWs Vivado/Vitis ...

environments. Support coverage closure and integration of VIP for networking protocols. Key Skills: UVM, constrained-random verification, testplan/coverage sign-off 100Gb Ethernet, PCIe Gen5, AMBA/AXI Python Scripting and CI/CD-based regression workflows Git proficiency Experience with Adaptive SoC design flows (Vivado/Vitis) Understanding ...

architecture, integration, timing closure, place-and-route (P&R), constraints and optimisation. The role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA, and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows. Key Responsibilities Design high-performance … using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready RTL meeting timing, P&R and integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocks Drive timing closure using Vivado toolchains Develop automation using Python/Tcl scripting Collaborate with hardware, SoC, firmware and integration ...

integration, timing closure, place-and-route (P&R), constraints and optimisation . The role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA , and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows . Key Responsibilities Design high-performance … using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready RTL meeting timing, P&R and integration requirements Implement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocks Drive timing closure using Vivado toolchains Develop automation using Python/Tcl scripting Collaborate with hardware, SoC, firmware and integration ...

RTOS. You’ll contribute to board bring-up, hardware/software co-debug, system verification, driver-level development, and support high-speed interfaces including PCIe and 100GbE. Collaboration with global engineering teams is central to this role. Key Skills Required Embedded software development in C/C++, plus scripting with … Strong experience with bare-metal, Yocto Linux, Zephyr, RTOS SoC software flows, co-simulation, hardware debug and board bring-up High-speed interface experience: PCIe, Ethernet, 100GbE, SerDes Proficient with Git, CI/CD pipelines Advantageous: familiarity with AMD Adaptive SoC, Vivado, Vitis What’s on Offer Long-term programme ...

RTOS . Youll contribute to board bring-up, hardware/software co-debug, system verification, driver-level development , and support high-speed interfaces including PCIe and 100GbE . Collaboration with global engineering teams is central to this role. Key Skills Required Embedded software development in C/C++ , plus scripting … Strong experience with bare-metal , Yocto Linux , Zephyr , RTOS SoC software flows , co-simulation, hardware debug and board bring-up High-speed interface experience: PCIe , Ethernet , 100GbE , SerDes Proficient with Git , CI/CD pipelines Advantageous: familiarity with AMD Adaptive SoC , Vivado , Vitis Whats on Offer Long-term programme with ...

implement UVM/SystemVerilog verification environments Deliver constrained-random verification and achieve coverage sign-off Verify high-speed interfaces including Ethernet (100G) and PCIe (Gen4/Gen5) Integrate and use Verification IP (VIP) Develop and maintain Python-based regression and CI workflows Collaborate with design, architecture, and SoC teams Essential … Skills & Experience Strong experience as a Verification Engineer/Design Verification Engineer Expert knowledge of UVM and SystemVerilog Experience with Ethernet, PCIe, AMBA/AXI Proven ownership of test plans and coverage closure Python scripting and Git-based workflows Experience in ASIC, SoC, or IP verification environments Desirable Experience with ...