2 of 2 Physical Design Engineer Jobs in the East of England

responsible for all stages from RTL to STA including logical equivalence checking (LEC) and conformal low power (CLP) checking. This will also include constraint and UPF development and debug. Physical implementation of Arm graphics processors using the entire implementation flow from RTL through place and route to STA. Supplying RTL feedback to designers via Jira to improve PPA and … ll need to succeed Cadence: Genus, Innovus, Tempus, QRC & Conformal PnR Flow: Synthesis, LEC, CLP, Floorplan, Placement, CTS, PostCTS, Routing, STA Synopsys: Fusion compiler, Formality Synthesis, LEC Low power design techniques (power gating, DVFS etc.) Understanding in building flows and methodologies using scripting languages such as TCL, Python, Perl to support project development. What you'll get in return More ❯

joined SoftBank Group - bringing large and ongoing investment from one of the world's leading backers of innovative AI companies. Job Summary We are looking for high-quality silicon physical design engineers to complement our existing exceptional team. We have a range of roles available with focus on those with extensive ranges of skills and experience although exceptional … and problem solutions. You will become part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. The Team The physical design team sits within the wider silicon design team which includes RTL, verification and DFT and with whom we collaborate extensively. Our work additionally involves strong links … product engineering. We are responsible for working with those teams to create high-quality RTL and then to build the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips More ❯