Senior Design Verification Engineer
- Hiring Organisation
- Intellectual Capital Resources
- Location
- Bristol, UK
- Employment Type
- Full-time
company who bring large and ongoing investment from one of the world's leading backers of innovative AI companies! SW Verification experience with Python, C/C++ is welcome alongside the traditional UVM based Verification. Responsibilities and duties Verification activities within the verification team Ensuring good communication between sites Verification … find root causes of deep and complex issues Experience of the verification process applied in CPU and/or ASIC environments System Verilog, Python, C++, Linux UVM SVA LLVM, GCC SGE or other DRMS XML and XPath/XSLT Benefits In addition to a competitive salary, you can expect flexible ...