2 of 2 SystemVerilog Jobs in Northern Ireland

Eastern Europe. You will design and develop high-performance IP cores while collaborating with various teams. Requirements include strong experience in SystemVerilog RTL design and familiarity with FPGA design flows. The role offers a contract duration of 6 months with a daily rate between €200 - €250. #J-18808-Ljbffr ...

fully remote opportunity open to candidates based in the UK (including Belfast) and Eastern Europe. The ideal candidate will have deep expertise in SystemVerilog RTL design and a strong understanding of FPGA design flows, including place & route and timing closure.Key Responsibilities Design and implement high-performance, synthesis-ready IP cores … using SystemVerilog RTL Develop IP for high-speed interfaces such as 100Gb Ethernet, PCIe Gen5, and AMBA/AXI Drive FPGA/Adaptive SoC design flow including synthesis, place & route (P&R), and timing closure Optimize designs for performance, area, and power Work closely with verification, system, and software teams ...