Sr. Systems Validation Engineer (SerDes / Physical Layer)
- Location
- Farnborough, England, United Kingdom
Error Rate Tester) DCA PNAX Perform: Eye diagram measurements Jitter tolerance testing Tune PHY parameters Enable debug hooks (register access, logging) Able to test a Stressed eye Validation of MDA Chipsets verifying functional and performance metrics Development and ownership of chip and system test plan with collaboration … development and test teams Development of test automation in Python for the chip and system test plans Investigation of root cause of test case failures and providing corrective action in conjunction with the development teams Execution, development and planning of Chip & System tests and Contribute ...