2 of 2 UVM Jobs in Bedfordshire

genetic algorithms Auto-generated code using model-driven engineering using MATLAB and Simulink tools Design tools such as Xilinx, TCL, Verilog, System Verilog and UVM Derivation of detailed Firmware requirements and architecture from system requirements A structured approach to firmware design (RTCA DO-254 or similar) Experience required: FPGA architectures ...

profile Qualifications Degree or better in Electronic Engineering, Computer science, or related subject Skills and Experience Experience in Verilog/SystemVerilog (essential) UVM (Universal Verification Methodology) is a must-have, experience with Formal Verification would be an advantage Experience in C/C++, Python, Perl, TCL for scripting and testbench ...