2 of 2 UVM Jobs in Reading

role, shaping the future of the verification team. What You'll Need: In-depth understanding of verification flows, test plans, and strategies. Expertise in constrained-random SystemVerilog testbenches using UVM or VMM. Experience in creating and examining functional coverage and writing SystemVerilog assertions. Skills in debugging RTL and gate-level simulation failures and firmware. Familiarity with bug tracking tools like More ❯

to production and delivery/tape-out, including performance review, analysis, costing, and optimisation Understanding of the product's design & verification needs, standardisation, adherence to frameworks and methodolgies e.g. UVM Excellent communicator, with a keen interest in team collaboration and a clear approach to the design & development process Bonus/"Nice-to-have" skills Digital Video processing/video compression More ❯