2 of 2 UVM Jobs in Reading

improved. What They're Looking For Experience managing or leading digital verification engineers Strong background in the verification of complex ICs Strong SystemVerilog and UVM experience, with knowledge of assertions and coverage-driven verification Experience developing verification strategies and using metrics such as code and functional coverage Ability to support ...

activities: demos, technical evaluations, benchmarks, methodology guidance Improve customer verification flows and testbench architectures Debug RTL/gate‐level simulation issues and SystemVerilog/UVM environments Analyse functional and code coverage Develop and debug SystemVerilog assertions Collaborate with Sales to grow adoption and identify new opportunities Act as the technical … voice of the customer to R&D What You’ll Need: Typically requires 8–13 yearsof relevant experience Strong knowledge ofVerilog/SystemVerilog, UVM, coverage, and assertions Experience in customer interaction, pre‐sales, or technical support is a plus Strong problem‐solving and communication skills Bachelor’s degree inComputer Engineering ...