10 of 10 Verification Engineer Jobs in the South West

Development Verification Engineer £55,000 - £65,000 + Training + Progression + 10% Bonus Bristol - Hybrid Are you a Development Verification Engineer or similar with expertise in SystemVerilog and UVM, seeking an autonomous role where your work directly contributes to the success of a leading semiconductor company, with opportunities for career growth, ongoing development, and the … strong global presence, they support clients in driving efficiency, safety, and sustainability across critical industries. In this role, you will develop and maintain SystemVerilog, UVM test benches, create new verification components, debug test cases, define functional coverage models, while supporting test bench architecture and design reviews using industry standard EDA tools. This is a full-time role, Monday to … Friday, 09:00AM - 17:00PM, with two days per week working from home. This role would suit a Development Verification Engineer with SystemVerilog and UVM skills, looking to join a world-leading semiconductor company with clear progression, specialist training, and the opportunity to boost earnings through a company bonus. The Role: Take the lead in creating and integrating More ❯

Development Verification Engineer £55,000 - £65,000 + Training + Progression + 10% Bonus Bristol - Hybrid Are you a Development Verification Engineer or similar with expertise in SystemVerilog and UVM, seeking an autonomous role where your work directly contributes to the success of a leading semiconductor company, with opportunities for career growth, ongoing development, and the … strong global presence, they support clients in driving efficiency, safety, and sustainability across critical industries. In this role, you will develop and maintain SystemVerilog, UVM test benches, create new verification components, debug test cases, define functional coverage models, while supporting test bench architecture and design reviews using industry standard EDA tools. This is a full-time role, Monday to … Friday, 09:00AM - 17:00PM, with two days per week working from home. This role would suit a Development Verification Engineer with SystemVerilog and UVM skills, looking to join a world-leading semiconductor company with clear progression, specialist training, and the opportunity to boost earnings through a company bonus. The Role: Take the lead in creating and integrating More ❯

Development Verification Engineer 55,000 - 65,000 + Training + Progression + 10% Bonus Bristol - Hybrid Are you a Development Verification Engineer or similar with expertise in SystemVerilog and UVM, seeking an autonomous role where your work directly contributes to the success of a leading semiconductor company, with opportunities for career growth, ongoing development, and the … strong global presence, they support clients in driving efficiency, safety, and sustainability across critical industries. In this role, you will develop and maintain SystemVerilog, UVM test benches, create new verification components, debug test cases, define functional coverage models, while supporting test bench architecture and design reviews using industry standard EDA tools. This is a full-time role, Monday to … Friday, 09:00AM - 17:00PM, with two days per week working from home. This role would suit a Development Verification Engineer with SystemVerilog and UVM skills, looking to join a world-leading semiconductor company with clear progression, specialist training, and the opportunity to boost earnings through a company bonus. The Role: Take the lead in creating and integrating More ❯

Junior Development Verification Engineer (Training and Progression) £30,000 - £35,000 + Training + Progression + 10% Bonus Bristol - Hybrid Are you an aspiring Verification Engineer looking to grow your expertise in SystemVerilog and UVM within a world-leading semiconductor company offering industry-leading training, structured progression, and the opportunity to increase your earnings through a … in the billions and a strong global presence, they support clients in driving efficiency, safety, and sustainability across critical industries. In this role, you'll work closely with experienced verification engineers to develop and maintain SystemVerilog - UVM test benches, assist in creating and integrating new verification components and debugging test cases. You'll receive hands-on training, tailored … development plans, and support to enhance your technical expertise, strengthen your understanding of EDA tools, and progress toward more senior verification roles as your experience grows. This is a full-time role, Monday to Friday, 09:00AM - 17:00PM, with two days per week working from home. This position would suit an aspiring Verification Engineer with foundational More ❯

Validation & Verification Engineer (V&V) Help shape the next generation of defence technology.I’m looking for a Validation and Verification (V&V) Engineer to play a key role in developing and delivering advanced Command & Control (C2) sub-systems – the central intelligence behind modern defence systems.You’ll be part of a team pushing technological boundaries, taking ownership … across the full development lifecycle – from initial design concepts to field deployment. As a V&V Engineer , your work will directly influence national security by ensuring that these mission-critical C2 systems perform flawlessly under pressure. In the role, you will: Define and execute Validation and Verification strategies for complex C2 systems. Lead V&V planning, ensuring requirements … are rigorously tested and validated. Develop detailed test scenarios and success criteria to support Validation and Verification outcomes. Collaborate with system and design engineers to implement effective V&V processes. Support ongoing Validation and Verification reviews, audits, and documentation across all project phases. You will have: A background in systems engineering or the design of software-intensive systems. More ❯

Subject - Senior Product Verification & Test Engineer Location - Onsite at the Paignton office Salary - Competitive + Benefits Benefits - Annual Bonus, 25 days annual leave (increasing to 30 with length of service), 4 x life insurance, employer pension contributions starting from 6% up to 14%, single private medical insurance and Medicash plan The Client - A global leader in advanced technology … simulation systems, many of which comprise radio frequency signal generators plus computer systems running complex application software; all designed in-house. The Candidate - You will be an experienced Product Verification and Test Engineer, comfortable working with RF lab equipment and test automation. You should bring strong skills in LabVIEW and/or Python, with the ability to troubleshoot … technical issues and deliver solutions to complex problems. A background in digital communications, RF systems, or GNSS is highly desirable. The Role - As a Senior Product Verification & Test Engineer, you will play a key role in the engineering team, focusing on verification and automation of both current and next-generation Positioning test solutions. Duties - Setup and perform More ❯

client is a globally recognised semiconductor company developing a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic … shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA More ❯

client is a globally recognised semiconductor company developing a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic … shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA More ❯

client is a globally recognised semiconductor company developing a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap. They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic … shift in architecture, making it an exciting time to join. Principal Verification Engineer Responsibilities: Develop and maintain SystemVerilog UVM testbenches for complex IPs. Lead the creation of new UVM verification components and contribute to testbench architecture Debug test failures and define functional coverage models to ensure sign-off quality. Work closely with designers and contribute to verification strategy during design and concept phases. Improve verification efficiency and ensure compliance with functional safety and quality standards. Requirements: Minimum 5 years of IP-level verification experience using SystemVerilog UVM. Strong understanding of UVM methodology, SVAs, and verification metrics. Ability to interpret complex design specifications and create robust verification environments. Proficiency in industry-standard EDA More ❯

Bristol The Sea Ceptor Weapon Systems team is expanding and seeks a Systems Engineer to deliver verification activity to support multiple customers. Salary: Up to £57,000 Depending on Experience Dynamic (hybrid) working: 2-3 days per week on-site due to workload classification Security Clearance: British Citizen or a Dual UK national with British citizenship. Restrictions and … is enabling the delivery of Sea Ceptor to multiple customers concurrently, whilst managing adaptations for an increasing number of export customers. This role is within the Weapon Systems Design & Verification team, delivering Verification activities to support multiple customers (both export and domestic) within Sea Ceptor. This will consist of task planning, budgeting and management to ensure the activities … to, and the review of, Subsystem evidence and outputs to enable Systems activities. Non-compliance generation, maintenance and reporting. Certification and Modification Register maintenance and reporting. Task management of Verification and Validation Activities Support to the generation of documentation (e.g. Trials Requirement Documents and Product Trials Clearance Certificates) and closure of Reviews (e.g. Regression Test Panels) to enable trials More ❯