3 Senior Verification Engineer Jobs with Hybrid or WFH Options

ASIC Verification Engineer - Bristol Hybrid working model and a fantastic compensation package. As a Digital Verification Senior Staff Engineer, you will work within the IP Development team in Bristol, a team with a proven track record in successful IP deliveries into Automotive Microcontrollers. This is … Verilog – UVM testbenches and solve potentially complex problems related to test bench development Be responsible for developing right from scratch UVC components for new verification environments; Be responsible for defining and writing a functional coverage model; Debug failing test cases to root cause; Participate in reviews to ensure test … bench meets quality and is complete; Contribute to verification perspective in Design and Concept meetings; Ensure test bench meets sign-off targets, including coverage, functional safety and test bench qualification; Proactively help increase efficiency of verification activities and mitigate risks early; Contribute to enhancing Verification strategy and more »

the AI market - combining ultra low power for pattern recognition and image sensing components to develop cutting edge IP is looking to hire a Senior Digital IC/SOC Verification Engineer. As Digital IC verification Engineer you will be part of the design team, and responsible … realization of energy-efficient mixed-signal neuromorphic processors/SoCs for AI at the sensor edge. The team is looking for a staff/senior Digital SoC Verification Engineer to implement the verification methodology, and execute the verification plan ensuring that their processors/SoCs … the team members, in collaboration with our international team(s) The ideal candidates for this position will have: Delivered with (as applicable) SoC design verification, SystemVerilog languages (UVM, SVA, SFC), low power verification (UPF methodology), software/hardware co-verification (SystemC/C/C++), Interfaced with more »

FPGA/Embedded System Engineer We think you'll love this opportunity, even if we are slightly biased! As an experienced Design & Verification Engineer Engineer, you will be part of the hardware platform team that builds development platforms for leading CPU and System IP products, that … ability to apply your RTL design skills using SystemVerilog for FPGA and/or ASIC, together with an understanding of FPGA device architecture. For verification you will be using System-Verilog and possibly UVM, this will include coding System Verilog Assertions (SVA) checks, cover-properties, SV coverage groups etc. … Tcl, Make, bash etc will also be required.. Required Skills and Experience: Proven experience of delivering RTL designs in a SoC or FPGA. RTL Verification at both unit and system level, using SV including SVA. Experience of ASIC or FPGA synthesis tools. Unix/Linux skills including shell programming more »