SoC Design Verification Engineer

SoC Design Verification Engineer

Job Title: SoC Design Verification Engineer/Senior Design Verification Engineer
Location: Bristol & Cambridge, UK
Number of Positions: 20 (10 Bristol/10 Cambridge)
Contract Duration: 6 Months
Rate: £55 per hour (Inside IR35)
Working Model: Hybrid - 3 days onsite and 2 days remote
Experience: 5-20 Years
Notice Period: Immediate or maximum 2 weeks

Job Overview

We are looking for experienced SoC Design Verification Engineers to join Synopsys Inc. for a next-generation multi-die System-on-Chip (SoC) project.

The successful candidates will work on subsystem-level and SoC-level functional verification using SystemVerilog and UVM methodologies. The role also involves processor-based verification through Embedded C test programs running on processor cores.

Candidates should have strong debugging skills, hands-on UVM experience and the ability to enhance and maintain existing verification environments.

Key Responsibilities

• Perform subsystem-level and SoC-level functional verification.

• Develop, modify and debug SystemVerilog/UVM testbenches.

• Develop and execute Embedded C test programs for processor-based SoC verification.

• Execute regression tests, analyse failures and resolve simulation issues.

• Perform functional coverage analysis and drive coverage closure.

• Debug complex RTL simulation failures using waveform tools.

• Work with design teams to understand design changes and update verification environments.

• Support verification planning and sign-off activities.

Required Technical Skills

• Strong hands-on experience with SystemVerilog and UVM.

• Experience in SoC or subsystem-level design verification.

• Good understanding of constrained-random verification, assertions, scoreboards and functional coverage.

• Experience modifying, enhancing and debugging existing UVM testbenches.

• Experience with Embedded C test development and debugging.

• Good understanding of SoC architecture, ARM processors, bus protocols and register interfaces.

• Strong RTL simulation debugging and waveform analysis skills.

• Experience in regression execution and coverage closure.

• Working knowledge of Python, Perl or Shell scripting.

• Familiarity with version control systems and verification workflows.

Candidate Requirements

• 5-20 years of relevant design verification experience.

• Strong debugging and problem-solving capabilities.

• Experience working with complex RTL designs and large SoC verification environments.

• Ability to independently manage verification activities.

• Experience adapting existing verification environments rather than only developing new testbenches.