Senior FPGA Engineer
Bath, Somerset, South West, United Kingdom
Xeroth AI
Fixed PRF phase-aligned to PPS. Gate to a fixed IQ sample count per pulse. One packet per pulse with zero drift over long runs. Packet header framing: Compact metadata header with magic value, monotonic pulse index, latched time counter, and fixed sample count. AXI-Stream to DMA for PS handoff. AXI control for RF switching: Manual and Automatic modes More ❯
Employment Type: Contract
Posted: