Cambridge, Cambridgeshire, England, United Kingdom
MicroTECH Global Ltd
with Intel Quartus Prime Pro toolchainRTL design in Verilog/SystemVerilog and/or VHDL Tech Stack: Quartus Prime Pro, Vivado, ModelSim, QuestaVerilog, SystemVerilogC, C++, Python, Haskell, Erlang, TCLGit, Jira Desirables:PCI3 Gen 6 experience Experience with Intel/Altera Agilex 5E FPGAsVHDLExposure to compute-in-memory, functional or dataflow architectures UVM or equivalent verification experience More ❯
each) within a hierarchical GPU through the full PnR flow from RTL to STA for multiple milestone release cycles. Provide regular detailed feedback to RTL designers, log details in Jira, and communicate directly via email/IM to push the PPA and achieve project goals within the project time scale.Your blocks will have hierarchical dependencies, requiring close collaboration with … UPF development and debug. Physical implementation of Arm graphics processors using the entire implementation flow from RTL through place and route to STA. Supplying RTL feedback to designers via Jira to improve PPA and remove implementation bottlenecks. Collaborating with EDA vendors to solve tool issues and advance PPA. Planning and scheduling of own work inline with the project goals More ❯
