1 of 1 Contract Verilog Jobs in Cambridge

next-generation, multi-die System-on-Chip (SoC) design. Engineers will be responsible for subsystem-level and SoC-level functional verification using System Verilog/UVM methodology, as well as processor-driven verification using C-based test programs executing on Embedded processor cores. The role requires strong debugging and analytical … architecture, and the ability to efficiently adapt existing verification environments to evolving design requirements. Key Responsibilities- 1. Subsystem and SoC Functional Verification 2. System Verilog/UVM Testbench Reuse and Enhancement 3. Processor-Based C Test Development and Verification 4. Regression Execution, Debugging, and Coverage Closure 5. Verification Planning ...