4 of 4 Contract CI/CD Jobs in County Antrim

cutting-edge systems. As a Senior IP Design Engineer, you will design and implement SystemVerilog RTL, developing synthesis-ready IP targeting FPGA / Adaptive SoC platforms. You will own end-to-end design flow including RTL architecture, integration, timing closure, place-and-route (P&R), constraints and optimisation. … role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI / AMBA, and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI / CD workflows. Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA / ...

cutting-edge systems. As a Senior IP Design Engineer, you will design and implement SystemVerilog RTL , developing synthesis-ready IP targeting FPGA / Adaptive SoC platforms. You will own end-to-end design flow including RTL architecture, integration, timing closure, place-and-route (P&R), constraints and optimisation . … role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI / AMBA , and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI / CD workflows . Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA / ...

Senior Verification Engineer RF / DSP (Contract) Were working with a leading technology organisation seeking an experienced Senior Verification Engineer to support advanced RF and DSP signal-chain verification on a high-impact project. This is a hands-on contract role, ideal for someone with strong ASIC / … building and maintaining robust verification environments and validating complex algorithms. Key Responsibilities Develop and maintain UVM, class-based verification testbenches Verify DSP / RF signal-chain blocks including FFT, FIR filters and channelizers Integrate VIP and drive constrained-random and coverage-driven verification Automate regressions using Python scripting Work ...

debug embedded software on advanced SoC architectures , working across bare-metal, Yocto Linux and Zephyr RTOS . Youll contribute to board bring-up, hardware / software co-debug, system verification, driver-level development , and support high-speed interfaces including PCIe and 100GbE . Collaboration with global engineering teams … central to this role. Key Skills Required Embedded software development in C / C++ , plus scripting with Python and Bash Strong experience with bare-metal , Yocto Linux , Zephyr , RTOS SoC software flows , co-simulation, hardware debug and board bring-up High-speed interface experience: PCIe , Ethernet , 100GbE , SerDes Proficient ...