2 of 2 Contract RISC-V Jobs in East Anglia

architecture, TrustZone, TEE, exception handling, and interrupt processing. Experience with kernel profiling tools (perf, ftrace, eBPF, LTTng, SystemTap). Knowledge of RISC-V privilege specifications or Arm architecture reference manuals. Deep knowledge of power management frameworks, DVFS (Dynamic Voltage and Frequency Scaling), and CPU idle states. Understanding ...

understanding of speculative execution, branch prediction, and out-of-order execution. Strong programming skills in C, C++, Python, assembly languages (Arm64 assembly or RISC-V assembly), and scripting languages. Experience with cycle-accurate microarchitecture simulation and performance modelling. Desirables: Experience with gem5, Sniper, ChampSim, or other cycle-accurate ...