5 of 5 Contract Git Jobs in Northern Ireland

Linux , Zephyr , RTOS SoC software flows , co-simulation, hardware debug and board bring-up High-speed interface experience: PCIe , Ethernet , 100GbE , SerDes Proficient with Git , CI/CD pipelines Advantageous: familiarity with AMD Adaptive SoC , Vivado , Vitis Whats on Offer Long-term programme with high technical impact Opportunity ...

Expert knowledge of UVM and SystemVerilog Experience with Ethernet, PCIe, AMBA/AXI Proven ownership of test plans and coverage closure Python scripting and Git-based workflows Experience in ASIC, SoC, or IP verification environments Desirable Experience with Vivado/Vitis or adaptive SoC flows Embedded processor co-simulation ...

drive constrained-random and coverage-driven verification Automate regressions using Python scripting Work within CI/CD environments and version control using Git Support ASIC/SoC/FPGA verification flows Essential Skills & Experience Strong experience as a Verification Engineer/ASIC Verification Engineer Proven UVM and class-based … verification expertise Solid background in DSP verification (FFT, FIR, signal processing) Python for automation and regression Experience with SoC/ASIC/FPGA environments Git version control Desirable MATLAB experience Exposure to Vivado/Vitis or adaptive SoC flows Contract role | Market rate | Remote working If youre a senior ...

focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA, and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows. Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready RTL meeting … flow: synthesis, P&R, timing closure High-speed digital interfaces: 100GbE/PCIe Gen5/AXI Vivado/Vitis toolchain expertise Python/Tcl, Git, CI/CD experience Details Contract: 6 months + extension Location: Remote (UK) Start: ASAP Rate: Market rate If you are a Senior ...

focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA , and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows . Key Responsibilities Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC Deliver synthesis-ready … flow: synthesis, P&R, timing closure High-speed digital interfaces: 100GbE/PCIe Gen5/AXI Vivado/Vitis toolchain expertise Python/Tcl, Git, CI/CD experience Details Contract: 6 months + extension Location: Remote (UK) Start: ASAP Rate: Market rate If you are a Senior ...