1 of 1 Contract Verification Engineer Jobs

Responsibilities- 1. Subsystem and SoC Functional Verification 2. System Verilog/UVM Testbench Reuse and Enhancement 3. Processor-Based C Test Development and Verification 4. Regression Execution, Debugging, and Coverage Closure 5. Verification Planning and Collaboration Required Technical Skills Essential Skills Strong hands-on experience in digital … design verification using System Verilog and UVM. Experience working with existing UVM testbenches, including modifying, extending, and debugging reusable verification components. Good understanding of constrained-random verification, functional coverage, assertions, scoreboards, and checkers. Experience in subsystem-level or SoC-level functional verification. Strong understanding of SoC architectures ...