7 of 7 Permanent Electronic Design Automation Jobs in Cambridge

Overview Qualcomm is seeking an experienced CPU Clock Physical Design Engineer to join the Nuvia Data Center CPU team in Cambridge, UK. The team develops next‐generation, high‐performance, power‐efficient custom CPU technology for advanced compute and server‐class platforms that will transform the industry. In this role … hold closure, and signoff quality. Ability to debug complex clocking issues across implementation, timing, power, noise, variation, and circuit domains. Experience with industry‐standard EDA implementation and signoff flows for physical design, timing analysis, power analysis, and physical verification. Strong communication skills and ability to work effectively with global ...

operating systems (in Rust and C). - Compilers, code generators, and linters. - Simulators and emulators (e.g. QEMU). - Electronic design automation (EDA) tools. - Performance and code size analysis. - Cloud-based infrastructure (such as continuous integration pipelines) Requirements : - Solid experience with C or Rust. - Strong algorithmic and problem …/CD for embedded or systems software. - Strong knowledge of computer architecture; some experience with assembly languages (x86, RISC-V); familiarity with hardware design is a plus. - Good knowledge of Linux. - Experience contributing to open source projects. - Higher degree levels and academic research experience are highly valued. ...

Overview Qualcomm Technologies International Ltd is seeking talented Physical Design Engineers to join the Nuvia CPU team in Cambridge, UK. The team develops next‐generation, high‐performance, power‐efficient custom CPU cores for advanced compute and server‐class platforms. The role ranges from Senior Engineer to Staff Engineer, with … trade‐offs between timing, power, area, congestion, and routability. Knowledge of high‐performance and low‐power implementation techniques. Hands‐on experience with industry‐standard EDA tools for synthesis, place and route, STA, power analysis, physical verification, and sign‐off (e.g., Genus, Innovus, Fusion Compiler, PrimeTime, Tempus, Voltus, RedHawk, Conformal). ...

perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE Are you an accomplished Physical Design leader passionate about pushing the boundaries of microprocessor design? Do you thrive on optimizing for Power, Performance, and Area (PPA) while leading dynamic … problem‐solving skills, coupled with meticulous attention to detail. Strong communication skills (written, verbal, and presentation) and excellent time management. Proficiency with industry‐standard EDA tools for Physical Design and Signoff flows, such as: Synopsys FusionCompiler, PrimeTime, StarRC Cadence Innovus Mentor Graphics Calibre Apache Redhawk Demonstrated experience leading technical ...

dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible … embedded products.* Preferred Skills and Experience: Master’s degree in computer engineering, electrical engineering, or a related field.* Experience with industry-leading SoC EDA tools and flows.* Knowledge of security features and related design principles.* Background in validation methodologies, including debugging on FPGA and silicon IC boards.**Travel Time ...

refactor support). Collaborate with Arm Engineering teams to capture real engineering struggles and turn them into clear requirements. Build quick prototypes and evaluate EDA AI tools, to validate feasibility and quantify impact. Drive adoption as a change leader: run demos/workshops; Contribute onboarding guides; Identify and remove adoption … verification methodology: Deep understanding of RTL design, interfaces between RTL, testbench and Verification IP, experience with debugging compile and simulation issues. Experience with EDA vendor tooling: Domain knowledge of at least one (of the three major) EDA vendor toolset. AI tooling fluency: Practical experience using AI for engineering automation ...

will have proven experience in delivering industry‐leading verification quality and productivity under tight schedules. In this role the candidate will collaborate with architecture, design and central formal verification teams to define our formal verification roadmap, strategy, methodology, infrastructure and expand formal verification adoption through project execution. The candidate … engines and use cases Proven expertise in system Verilog assertion and abstract model development Expert user of formal verification tools from both academia and EDA vendors (JasperGold, VC formal, Murphi, theorem prover) Proven track record of delivering high quality verification under tight schedule for modern, large‐scale processor design ...