8 of 8 Permanent Design Engineer Jobs in Cambridgeshire

FPGA Design Engineer seeking a challenging career move where you can contribute to the very latest imaging and augmented reality systems, designing and implementing FPGA based SoC systems? Hybrid working (up to 3 days per week from home) and very generous salary on offer. This award-winning Technology … company seeks a well qualified FPGA Engineer with SoC design and Integration skills, RTL Verification experience (SystemVerilog, VHDL) and Python knowledge. In this role the successful FPGA Design Engineer will write timing constraints and where necessary modify designs to close timing; working closely with hardware, software ...

Title : Junior Electronic Design Engineer Location : Cambridge (Hybrid Working - 3 Days On-Site Per Week) Salary : £35,000 - £45,000 + Bonus & Benefits (Depending on Experience) Please Note : All Applicants must have the right to work in the UK without the need for VISA sponsorship … future. Role Overview: Zenovo are looking for an Junior Electronic Design Engineer to join their client in Cambridge who design and manufacture globally recognised consumer electronics.An ideal candidate will have at least 1-Year of Experience outside of University however we are happy to consider candidates ...

Leader - Base, RSUs, Bonus - 5 days onsite A rare opportunity has opened for a CPU ASIC Design Engineer to join one of the world’s most influential semiconductor companies at its flagship UK design centre in Cambridge. You’ll become part of an elite engineering organisation developing … advanced wearable platforms used by millions around the globe. This role places you at the centre of CPU innovation — working alongside leading architects and design teams to shape high-performance, low-power processor technology from early concept through to silicon delivery. As a CPU ASIC Design Engineer ...

week, flexible working, including up to 3 days per week working from home Salary: Competitive Job Reference: 36054 We are seeking an experienced FPGA Design Engineer to join our client's expanding development team, based a few miles north of Cambridge. You will be working on high performance … Requirements: - Strong knowledge of SystemVerilog - Experience with Python - Proven background in RTL verification - Ability to write and validate timing constraints - Understanding of low power design principles - Experience writing module specifications and reviewing technical documentation - Code and documentation review to established standards - Familiarity with: * Linux command line * Version control systems ...

Role Overview: Have in depth knowledge and understanding of best-practice digital design methods. Be an expert at executing designs via a fully synthesised digital design flow with RTL and logic synthesis. Be fully conversant with the SystemVerilog standard and digital EDA tools. Be familiar with … constraints and the automatic place-and-route flow for the physical design. Understand the importance of production test and have experience of design methods to maximize digital test coverage such as scan. Have experience of design techniques for optimising digital power consumption. Have experience of debugging digital functions ...

Senior FPGA RTL Engineer Location: Cambridge (Flexible/Hybrid) Salary: £150k+ bonus My client is an innovative technology company developing cutting-edge, high-performance systems for demanding real-time applications. As part of continued growth and investment in next-generation platforms, they are seeking an experienced Senior FPGA … Engineer to join their engineering team. This is an excellent opportunity to work on technically challenging projects where performance, reliability and optimisation are critical. You'll play a key role in shaping future FPGA architectures and mentoring engineers within a highly skilled development environment. The Role As a Senior ...

processors—including CPUs, GPUs, and neural accelerators and this is where you come in! You will be joining a Fabric IP company as a Design Verification Engineer, contributing your strong background in developing testbenches and writing test sequences for complex IPs. In this role, you will play …/SystemVerilog code to implement the test plan, checkers, and scoreboards Collaborate with software teams to define and implement configurable testbenches Work with design teams test plans, failure debug, coverage, etc Qualifications and preferred skills BS, MS in Electrical Engineering, Computer Engineering or Computer Science 5+ years and current ...

exciting opportunity has just opened for a Senior/Lead Verification Engineer to join a cutting-edge team in Cambridge, UK, driving innovation in next-gen semiconductor projects Our client is expanding their DV team at a key growth stage, offering a rare opportunity to join early and genuinely … collaboration with world-leading partners such as Google. This is real silicon used as a foundation for secure and scalable compute systems. Key Responsibilities Design, implement, and debug block/system-level tests and testbenches using SystemVerilog and UVM Develop test and coverage plans for new and updated designs ...