4 of 4 Permanent Actel Jobs in Edinburgh

Senior or Principal Firmware / FPGA Engineer

Hiring Organisation
Leonardo DRS
Location
Edinburgh, Midlothian, United Kingdom
Salary
£ 50 K
Verilog an advantage but not essential. Implementing high speed, multi-frequency clocking architecturesDesign with FPGA technologies from either AMD(Xilinx), Intel (Altera) or Microsemi (Actel).Use of Xilinx Vivado or Altera Quartus II/Quartus Prime is an advantageExperience of FPGA architectures such as SoC system-on-chip (e.g. ...

Principal FPGA Engineer

Location
City of Edinburgh, Scotland, United Kingdom
Verilog. Experience with Mentor Graphics tools, including HDL Designer, ModelSim/Questa and Precision. Knowledge of Xilinx, Intel/Altera or Microsemi/Actel design flows, including ISE, Vivado and Quartus. Experience specifying timing and area constraints for FPGA place and route. Independent FPGA verification experience using VHDL. Experience ...

Senior / Principal FPGA Engineer

Location
City of Edinburgh, Scotland, United Kingdom
other disciplines Experience with Mentor Graphics tools, including HDL Designer, ModelSim/Questa and Precision Familiarity with Xilinx, Intel (Altera) and/or Microsemi (Actel) design flows, including Vivado, Quartus and ISE Experience with timing/area constraints, synthesis and Place & Route Experience with independent FPGA verification using VHDL ...

Senior / Principal FPGA Engineer

Hiring Organisation
Quest Global Services
Location
Edinburgh, Midlothian, United Kingdom
Salary
£ 70 K
Verilog Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim/Questa and Precision Familiar with Xilinx/Intel (Altera)/Microsemi (Actel) design flows (ISE, Vivado, Quartus) and third-party synthesis toolsExperience in specifying timing and area constraints for efficient FPGA Place and Route.Independent verification using … Verilog Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim/Questa and Precision Familiar with Xilinx/Intel (Altera)/Microsemi (Actel) design flows (ISE, Vivado, Quartus) and third-party synthesis toolsExperience in specifying timing and area constraints for efficient FPGA Place and Route.Independent verification using ...