Design Verification Engineering Intern
- Location
- City of Edinburgh, Scotland, United Kingdom
computer architecture. Coursework or practical exposure to: Verilog/System Verilog or VHDL RTL design principles Simulation workflows Familiarity with scripting languages (Python, Perl, Tcl, Bash, etc.). Good analytical and debugging skills. Strong communication and willingness to learn in a fast‐paced engineering environment. Nice‐to‐Have Skills Experience ...